See Also

All clock signals in a design should be global signals. Clock signals that are mapped to regular logic can affect the performance of the design.

You can use the Global Signal logic option to specify that a clock signal is a global signal. If a design contains more clock signals than you can specify as global signals for the current device, you should reduce the number of clock signals in the design.

You can also use the Auto Global Clock logic option to allow the Fitter to automatically chose clock signals as global signals; the Fitter may automatically choose all the clock signals as global signals.

This rule applies only to designs that the Fitter has processed during a compilation.

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