Converting Between Types

Question: I am modelling and synthesizing (with Synopsys) a bit level multiplier. A correction factor is added to the output, whose value is calculated from generics of type integer. The output port is of type Bit_vector, so I am unable to perform a straight addition of the correction factor to the output result, and there is no type conversion function from Integer to Bit_vector. Is there any alternative method of performing this mixed-type operation?

Answer: In a just world, this kind of operation should be very straightforward. But who said VHDL was just? As you say, VHDL does not provide any built in type conversion from Integer to Bit_vector, nor any built in operators to add integers to Bit_vectors. However, there are suitable functions around, if only you can find them!

If you wish to stick with type Bit_vector, the solution is rather awkward using the current generation of packages from Synopsys, ie:

  use IEEE.Std_logic_1164.all;
  use IEEE.Std_logic_arith.all;
  use IEEE.Std_logic_unsigned.all;
  ...
  Result <=
    To_BitVector(                     -- Std_logic_1164
      To_StdLogicVector(Result)       -- Std_logic_1164
      +                               -- Std_logic_unsigned
      Conv_Std_logic_vector           -- Std_logic_arith
          (Correction,Result'Length));

Horrible, huh? There are other variations on this theme, but none of them are much better. But then to be fair, these packages are not intended to support arithmetic on Bit_vectors. The simplest way forward may well be to abandon the type Bit_vector in favour of the IEEE standard data type Std_logic_vector. The solution then becomes much more acceptable:

  use IEEE.Std_logic_1164.all;
  use IEEE.Std_logic_unsigned.all;
  ...
  generic (Correction: Integer);
  port (Result: buffer Std_logic_vector);
  ...
  Result <= Result + Correction;

This works because the package Std_logic_unsigned (provided by Synopsys) overloads the plus operator to add a Std_logic_vector (interpreted as an unsigned binary number) to an integer, returning a result of type Std_logic_vector.

A negative point against the above solutions is that they use a package provided by a particular synthesis tool vendor, which limits the portability of the VHDL code between synthesis tools. It would be preferable to have one VHDL package providing arithmetic operations on vector types, and supported by all simulation and synthesis tools. This is where the IEEE come charging to the rescue. There is such a standard, it is called IEEE Std 1076.3, and it includes amongst other things two packages NUMERIC_BIT and NUMERIC_STD for this very purpose. The bad news is that the standard is still at the draft stage, and it will be some time before it is finalised and widely supported.

Using the draft 1076.3 standard, the solution is as above, except that IEEE.Std_logic_unsigned is replaced by IEEE.Numeric_std, and Result is of type Unsigned.

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