From the start of our first VHDL training programme in 1990, the Doulos goal has been to enable engineers to be successful with the application of VHDL and Verilog rather than presenting the languages as an end in themselves. This has required a sustained commitment to a high quality of course material and provision and a determination to avoid gimmicks and compromises.
Worldwide Course Schedule
Comprehensive VHDL for FPGA/ASIC
Verilog
for FPGA and ASIC Design
AVT, Advanced VHDL Techniques
Advanced
VHDL for Synthesis
Comprehensive VHDL for Systems
VHDL Seminar for Managers
Made-to-measure
Training
Copyright 1995-1997 Doulos
This page was last updated 27th February 1997
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