EE 8063 Parallel Computing Architecture

This is the home page for Parallel Computing Architecture I course for Fall '98. A previous computer architecture course such as EE 4713 is a prerequisite for this course. I am assuming that you are familiar with pipelined architectures; the course will start with a review of pipelined CPUs and go from there. We will start with Instruction Level Parallelism (superscalar and VLIW architectures) and move towards multiple CPU systems, particularly MIMD architectures.

Textbook

The textbook will be Advanced Computer Architectures (Sima, Fountain, Kacsuk). Other references are Computer Architecture, Pipelined and Parallel Processor Design (Flynn) and Computer Architecture, A Quantitative Approach (Hennessey and Patterson).

The order of Chapter coverage in the textbook will be:

  1. Chapter 4 - Introduction to Instruction Level Parallelism
  2. Chapter 5 - Pipelined Processors (this should be review). Will have a VHDL modeling assignment with this chapter.
  3. Chapter 6 - VLIW Architectures
  4. Chapter 7 - SuperScalar Processors (will have a VHDL modeling assignment with this chapter)
  5. Chapter 8 - Branch Processing for ILP Architectures
  6. Memory Architectures (Review of cache strategies) - Cache simulator assignment
  7. Chapter 16 - Multi threaded Architectures
  8. Chapter 17 - Distributed Memory Architectures
  9. Chapter 18 - Shared Memory Architectures
  10. Future Directions - Processor and Memory

At this point, if we have time left in the semester we will look at selected topics from SIMD architectures (Chapters 10-14).

Skills

  1. VHDL Modeling - we will do some VHDL modeling of the concepts we discuss in class. I will provide the skeletons of the models that we will use in class but I will expect you to be able to fill in internals.
  2. I also expect students to be able to have general programming skills as some exercises can be completed via any programming language.

Policy

The grading policy will be:

 

All external assignments are to be INDIVIDUAL work. You may discuss the assignments with other students but you may not share any work, or show anybody your work as examples of how to do something. Any violations of this policy will result in the assignment of a failing grade for the ENTIRE course.

Office Hours

If I am not in class, I can be found in ERC Rm 231. My email is reese@erc.msstate.edu, phone is 5-3670. Please feel free to drop in anytime. Before making a trip to the ERC, please call and see if I am in - I often get dragged into miscellaneous meetings that can occur anytime.

Lectures

This material is taken from the textbook Advanced Computer Architectures (Sima, Fountain, Kacsuk).

Other Links

Assignments