VLIW Architectures
Keeping Execution Units Busy
Multi-Ported Register File Design has Limits
Multiported Register Files (cont)
Solving the Register File Bottleneck
Register File Communication
Register File Communication (cont).
Instruction Compression
When are instructions decompressed?
Importance of the Compiler
TMS320C6X CPU
TMS320C6X CPU (cont).
Instruction Encoding
Fetch Packet to Execute Packet Expansion
Fetch Packet to Execute Packet Expansion (cont.)
Pipeline
Pipeline (cont)
PPT Slide
Trimedia TM-1000 (cont)
Trimedia TM-1000
Email: reese@erc.msstate.edu
Home Page: http://www.erc.msstate.edu/~reese
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