Xilinx에서 무료로 제공하는 HDL coding관련 online 교육자료.  바로가기 부분을 click하시면 해당 강의 동영상을 보실 수 있습니다.  (영어로 진행되는 강의입니다.)

 

Basic HDL Coding Techniques

 Learn how to describe primary coding techniques for FPGAs, including basic design guidelines that successful FPGA designers follow and explain proper coding techniques for combinatorial and registered logic, describe primary coding techniques for FPGAs, including basic design guidelines that successful FPGA designers follow, as well as, Finite State Machine design and building pipeline stages.

강의시간: 00:46:27
바로가기: http://www.xilinx.com/training/languages/basic-hdl-coding-techniques-video.htm

 

Spartan-3 FPGA HDL Coding Techniques

 Learn how to code properly for FPGA registers, SRLs, and other dedicated resources. These techniques will enable you to build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs. code properly for carry logic and memory resources. You will also know how to manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs.

After completing this module, you will know how to:

• Code properly for FPGA registers, SRLs, and other dedicated resources
• To build an efficient, high-speed FPGA design for the Spartan®-3 FPGA and other 4-input, LUT-based FPGAs
• Code properly for carry logic and memory resources
• To manage your control signal usage so that you can build an efficient, high-speed FPGA design for the Spartan-3 FPGA and other 4-input, LUT-based FPGAs

강의시간: 01:15:30
바로가기: http://www.xilinx.com/training/languages/spartan-3-hdl-coding-techniques-video.htm

 

Virtex-5 FPGA HDL Coding Techniques

 Learn how to code properly for Virtex-5 FPGA register resources. You will also know how to manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possiblel, code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA. You will also know how to manage your control signal usage so that you can build a high-speed FPGA design. Finally, you will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA.

After completing this module, you will know how to:

• Code properly for Virtex®-5 FPGA register resources
• To manage your control signal usage so that you can build a smaller FPGA design that will run at the highest system speed possible
• Code properly for 6-input LUT and block RAM resources in the Virtex-5 FPGA
• To manage your control signal usage so that you can build a high-speed FPGA design
• You will identify the most important considerations for migrating an existing design to the Virtex-5 FPGA

강의시간: 01:09:10
바로가기: http://www.xilinx.com/training/languages/virtex-5-hdl-coding-techniques-video.htm

 

Virtex-6 & Spartan-6 FPGA HDL Coding Techniques

 Learn how to code your register resources so your design will have fewer control sets and run at a higher system speed, avoid the most common coding mistakes that reduce device utilization and system speed, anticipate how your design will map to the register resources, code your design so you can infer more of the dedicated hardware resources, avoid the most common coding mistakes which hurt device utilization, reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR).

After completing this course, you will know how to:

• Code your register resources so your design will have fewer control sets and run at a higher system speed
• Avoid the most common coding mistakes that reduce device utilization and system speed
• Anticipate how your design will map to the register resources
• Code your design so you can infer more of the dedicated hardware resources
• Avoid the most common coding mistakes which hurt device utilization
• Reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR)

강의시간: 01:04:19
바로가기: http://www.xilinx.com/training/languages/virtex-6-and-spartan-6-hdl-coding-techniques-video.htm

 

What are FPGA Power Management HDL Coding Techniques

 After completing this course on FPGA Power Mangement HDL Techniques you will be able to explain how power is dependent on the HDL coding style you use, describe how your design’s power consumption is dependent on your use of control signals, explain how some common design techniques can improve your design’s power consumption, show how some common design techniques can improve your design’s power consumption.

After completing this training, you will know how to:

• Explain how power is dependent on the HDL coding style you use
• Describe how your design's power consumption is dependent on your use of control signals
• Explain how some common design techniques can improve your design's power consumption
• Show how some common design techniques can improve your design's power consumption

강의시간: 00:09:37
바로가기: http://www.xilinx.com/training/languages/what-are-fpga-power-management-hdl-coding-techniques-video.htm