작성일: 2021.11.26

6502 processor written in VHDL

The 6502, conceived in 1975, is a simple 8 bit microprocessor with one working register (A) and two index registers (X and Y).

As it's now over 20 years old the patent has expired and it can be used as a general purpose micro as part of larger more complicated systems inside FPGAs.

The 'Free-6502' core is an opcode compatible CPU core with the following basic features:

It is based on version 0.7 of the Free-6502 with a little additional work to implement BCD mode arithmetic.

One of the slightly amusing parts of the design is the use of an Excel spreadsheet to describe the microcode, which is then exported and recycled into the VHDL required for the CPU core.

With no special care taken towards optimising for area or speed, the default settings in the Xilinx Foundation M1.5 software produced a design with the characteristics as follows.

Implemented at 12.5MHz (using only a clk period constraint)

There are 3 possible downloads to choose from

  1. Foundation project - for use with the Xilinx Foundation M1.5 software, this should be unzipped into the C:\fndtn\active\projects\ per usual.
    It contains a simple schematic using the core; a testrom; and some i/o buffers.
    This can be used as a basis for other designs or at the very least as a quick way to evaluate the core with Xilinx family parts.
  2. Details of changes - a summary of the changes made to the original VHDL to add the BCD arithmetic to the arithmetic and logic unit (ALU).
    Also includes a simple test ROM and source code to validate the changes made compared with a real 6502.
  3. The original VHDL - suitable for use with other vendor's FPGA tools, archived here are as the original website seems to be offline.

©2009 SPROW [Updated 07-Aug-2009]


Source: http://www.sprow.co.uk/dump/index.htm#Free6502

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