This annex provides a summary of the syntax for VHDL. Productions are ordered alphabetically by left-hand nonterminal name. The clause number indicates the clause where the production is given.
abstract_literal ::= decimal_literal | based_literal [§ 13.4]
access_type_definition ::= access subtype_indication [§ 3.3 ]
actual_designator ::= [§ 4.3.2.2]
expression
| signal_name
| variable_name
| file_name
| open
actual_parameter_part ::= parameter_association_list [§ 7.3.3]
actual_part ::= [§ 4.3.2.2]
actual_designator
| function_name ( actual_designator )
| type_mark ( actual_designator )
adding_operator ::= + | - | & [§ 7.2]
aggregate ::= [§ 7.3.2]
( element_association { , element_association } )
alias_declaration ::= [§ 4.3.3]
alias alias_designator [ : subtype_indication ] is name [ signature ] ;
alias_designator ::= identifier | character_literal | operator_symbol [§ 4.3.3]
allocator ::= [§ 7.3.6]
new subtype_indication
| new qualified_expression
architecture_body ::= [§ 1.2]
architecture identifier of entity_name is
architecture_declarative_part
begin
architecture_statement_part
end [ architecture ] [ architecture_simple_name ] ;
architecture_declarative_part ::= [§ 1.2.1]
{ block_declarative_item }
architecture_statement_part ::= [§ 1.2.2]
{ concurrent_statement }
array_type_definition ::= [§ 3.2.1]
unconstrained_array_definition | constrained_array_definition
assertion ::= [§ 8.2]
assert condition
[ report expression ]
[ severity expression ]
assertion_statement ::= [ label : ] assertion ; [§ 8.2]
association_element ::= [§ 4.3.2.2]
[ formal_part => ] actual_part
association_list ::= [§ 4.3.2.2]
association_element { , association_element }
attribute_declaration : [§ 4.4]
attribute identifier : type_mark ;
attribute_designator ::= attribute_simple_name [§ 6.6]
attribute_name ::= [§ 6.6]
prefix [ signature ] ' attribute_designator [ ( expression ) ]
attribute_specification ::= [§ 5.1]
attribute attribute_designator of entity_specification is expression ;
base ::= integer [§ 13.4.2]
base_specifier ::= B | O | X [§ 13.7]
based_integer ::= [§ 13.4.2]
extended_digit { [ underline ] extended_digit }
based_literal ::= [§ 13.4.2]
base # based_integer [ . based_integer ] # [ exponent ]
basic_character ::= [§ 13.1]
basic_graphic_character | format_effector
basic_graphic_character ::= [§ 13.1]
upper_case_letter | digit | special_character| space_character
basic_identifier ::= letter { [ underline ] letter_or_digit } [§ 13.3.1]
binding_indication ::= [§ 5.2.1]
[ use entity_aspect ]
[ generic_map_aspect ]
[ port_map_aspect ]
bit_string_literal ::= base_specifier " [ bit_value ] " [§ 13.7]
bit_value ::= extended_digit { [ underline ] extended_digit } [§ 13.7]
block_configuration ::= [§ 1.3.1]
for block_specification
{ use_clause }
{ configuration_item }
end for ;
block_declarative_item ::= [§ 1.2.1]
subprogram_declaration
| subprogram_body
| type_declaration
| subtype_declaration
| constant_declaration
| signal_declaration
| shared_variable_declaration
| file_declaration
| alias_declaration
| component_declaration
| attribute_declaration
| attribute_specification
| configuration_specification
| disconnection_specification
| use_clause
| group_template_declaration
| group_declaration
block_declarative_part ::= [§ 9.1]
{ block_declarative_item }
block_header ::= [§ 9.1]
[ generic_clause
[ generic_map_aspect ; ] ]
[ port_clause
[ port_map_aspect ; ] ]
block_specification ::= [§ 1.3.1]
architecture_name
| block_statement_label
| generate_statement_label [ ( index_specification ) ]
block_statement ::= [§ 9.1]
block_label :
block [ ( guard_expression ) ] [ is ]
block_header
block_declarative_part
begin
block_statement_part
end block [ block_label ] ;
block_statement_part ::= [§ 9.1]
{ concurrent_statement }
case_statement ::= [§ 8.8]
[ case_label : ]
case expression is
case_statement_alternative
{ case_statement_alternative }
end case [ case_label ] ;
case_statement_alternative ::= [§ 8.8]
when choices =>
sequence_of_statements
character_literal ::= ' graphic_character ' [§ 13.5]
choice ::= [§ 7.3.2]
simple_expression
| discrete_range
| element_simple_name
| others
choices ::= choice { | choice } [§ 7.3.2]
component_configuration ::= [§ 1.3.2]
for component_specification
[ binding_indication ; ]
[ block_configuration ]
end for ;
component_declaration ::= [§ 4.5]
component identifier [ is ]
[ local_generic_clause ]
[ local_port_clause ]
end component [ component_simple_name ] ;
component_instantiation_statement ::= [§ 9.6]
instantiation_label :
instantiated_unit
[ generic_map_aspect ]
[ port_map_aspect ] ;
component_specification ::= [§ 5.2]
instantiation_list : component_name
composite_type_definition ::= [§ 3.2]
array_type_definition
| record_type_definition
concurrent_assertion_statement ::= [§ 9.4]
[ label : ] [ postponed ] assertion ;
concurrent_procedure_call_statement ::= [§ 9.3]
[ label : ] [ postponed ] procedure_call ;
concurrent_signal_assignment_statement ::= [§ 9.5]
[ label : ] [ postponed ] conditional_signal_assignment
| [ label : ] [ postponed ] selected_signal_assignment
concurrent_statement ::= [§ 9]
block_statement
| process_statement
| concurrent_procedure_call_statement
| concurrent_assertion_statement
| concurrent_signal_assignment_statement
| component_instantiation_statement
| generate_statement
condition ::= boolean_expression [§ 8.1]
condition_clause ::= until condition [§ 8.1]
conditional_signal_assignment ::= [§ 9.5.1]
target <= options conditional_waveforms ;
conditional_waveforms ::= [§ 9.5.1]