This page summarizes the results from the MICROSWISS Project TR-EZ-001 ``VHDL Library of Arithmetic Units''.

Lecture on Computer Arithmetic
VHDL Library of Arithmetic Units
Synthesis of Parallel-Prefix Adders
VHDL Mode for Emacs
VHDL Support

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Lecture on Computer Arithmetic

Abstract

A lecture was held and comprehensive lecture notes have been put together with the title ``Computer Arithmetic: Principles, Architectures, and VLSI Design''.

Lecture Notes

• R. Zimmermann, Computer Arithmetic: Principles, Architectures, and VLSI Design, Lecture notes, Integrated Systems Laboratory, ETH Z?ich, 1997.
  [contents, postscript (notes), postscript (slides), postscript (notes, letter format)]

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VHDL Library of Arithmetic Units

Abstract

A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed. The library contains components for a variety of arithmetic operations and for different speed requirements. The library components are implemented as circuit generators in parameterized structural VHDL code. Their modular and well-documented source code allows for simple usage and easy customization. Highly efficient circuit architectures are used, which are optimized for synthesis and cell-based design. The VHDL library is platform independent, and it provides circuits with comparable performance, but higher flexibility and a larger diversity of arithmetic operations compared to commercial data path libraries.

Publications

• R. Zimmermann, ``VHDL Library of Arithmetic Units'', in Proc. First Int. Forum on Design Languages (FDL'98), Lausanne, Switzerland, Sept. 1998.
  [abstract, postscript]


• R. Zimmermann, ``VHDL Library of Arithmetic Units'', Technical report no. 98/3, Integrated Systems Laboratory, ETH Z?ich, Jan. 1998.
  [abstract, postscript]


• R. Zimmermann, Binary Adder Architectures for Cell-Based VLSI and their Synthesis, PhD thesis, Swiss Federal Institute of Technology (ETH) Zurich, Hartung-Gorre Verlag, 1998.
  [abstract, postscript, postscript (letter format)]


• H. Kunz and R. Zimmermann, ``High-Performance Adder Circuit Generators in Parameterized Structural VHDL'', Technical report no. 96/7, Integrated Systems Laboratory, ETH Z?ich, Aug. 1996.
  [abstract, postscript]


• R. Zimmermann and H. Kaeslin, ``Cell-Based Multilevel Carry-Increment Adders with Minimal AT- and PT-Products'', submitted to IEEE Transactions on VLSI Systems.
  [abstract, postscript]

Download

• VHDL Library Package: arith_lib-1.0.tar.gz (size 77k), arith_lib-1.0.zip (size 247k),

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Synthesis of Parallel-Prefix Adders

Abstract

The class of parallel-prefix adders comprises the most area-delay efficient adder architectures - such as the ripple-carry, the carry-increment, and the carry-lookahead adders - for the entire range of possible area-delay trade-offs. The generic description of these adders as prefix structures allows their simple and consistent area optimization and synthesis under given timing constraints, including non-uniform input and output signal arrival times. In this work, an efficient non-heuristic algorithm for the generation of size-optimal parallel-prefix structures under arbitrary depth constraints was developed.
The algorithm for size and depth optimization of prefix structures bases on a series of simple local graph transformations. By applying such transformations using a straightforward graph traversal scheme, a prefix structure can be compressed to minimal depth or expanded to a given depth with minimal size. A size-optimal prefix structure for a given depth can be synthesized by first generating a serial-prefix structure, which then undergoes a compression and a depth-controlled expansion step. The algorithm uses no heuristics at all and thus is highly runtime efficient.
The developed algorithm can be used for the efficient synthesis of area-optimized adders for arbitrary timing constraints, including non-uniform signal arrival times, as found e.g. in the final adder of multipliers. A Java applet has been developed implementing the synthesis algorithm and a graphical user interface.

Publications

• R. Zimmermann, ``Non-Heuristic Optimization and Synthesis of Parallel-Prefix Adders'', in Proc. Int. Workshop on Logic and Architecture Synthesis (IWLAS'96), Grenoble, France, Dec. 1996, pp. 123-132.
  [abstract, postscript]

Download

• Java Applet

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VHDL Mode for Emacs

Abstract

Emacs is an extendable, self-documenting text editor which allows syntax-driven editing of source code for a variety of programming languages. In this work, an Emacs mode for editing VHDL source code was developed. The resulting VHDL Mode provides - among others - highlighting of VHDL syntax, automatic indentation, template insertion for many VHDL constructs, menu support, and source file compilation (syntax analysis).
VHDL Mode is implemented as an Emacs package containing a collection of Lisp functions and is compatible with GNU Emacs and XEmacs. It was assembled from existing smaller packages, improved, and extended by numerous additional functions.
VHDL Mode is made officially available on WWW and used worldwide by the VHDL design community. It has become part of GNU Emacs.
[snapshot]

Download

• Emacs VHDL Mode Home Page

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VHDL Support

Download

• VHDL'02 Syntax as HyperText
• VHDL'93 Syntax as HyperText
• VHDL'87 Syntax as HyperText
• VHDL-AMS Syntax as HyperText