Computer Aids for VLSI Design
Steven M. Rubin
Copyright © 1994

Appendix G: Index

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A-kind-of relation3.4
A-part-of relation3.4
Abstraction, see view
Acceleration
  graphics9.2
  timed9.4
Acoustic interference10.2
Active component1.4
Actor2.3
Ada8.2
Additive color space9.3
Address unit (EBES)E
Addressing, computer1.1
Algebra, geometry3.6
Algorithm
  D6.5
  environment2.3
  greedy4.2
ALI8.3
Alignment4.4
  marks4.6
Allocation, memory3.2
An-instance-of relation3.4
Analysis1.1
  dynamic5.1, 6.1
  functional verification5.5
  isolated-circuit detection5.4
  power estimation5.4, 6.5
  rule checking5.1, 5.3
  short-circuit detection5.4
  simulation5.1, 6.1, 11.5
  static5.1
  timing verification5.5
  tool1.1, 4.1
  transistor-ratio checking5.4
  verification5.1, 5.5
And plane4.2
Annotate (EDIF)D
APL8.2
Application-specific integrated circuit1.1
Arc
  EDIFD
  Electric11.2
  GerberA
  invisible11.4
  object3.5
  universal11.4
  unrouted11.4
Architect, machine2.1
Array
  gate4.2
  grid2.5
  reference (GDS II)C
  programmable logic4.2, 11.5
  storage/logic4.2
  uncommitted logic4.2
  Weinberger4.2
Arraydefinition (EDIF)D
Arrayrelatedinfo (EDIF)D
Artificial intelligence1.1
Artwork7.2
  alignment marks4.6
  compensation4.6
  critical dimensions4.6
  environment2.5, 11.4
  fiducial marks4.6
  pattern4.6
  scribe lane4.6
  target4.6
  technology (Electric)11.4
ASIC, see application-specific integrated circuit
Aspect ratio9.3
Asynchronous circuit1.3
Attribute3.2
Axiom2.3
B-spline curve9.2
Backtracking
  constraint8.3
  routing4.3
BASIC8.2
Batch
  change11.5
  integrated circuit7.3
Behavior1.3
  EDIF viewD
  -level simulation6.4
Bezier curve9.2
Bilevel display9.2
Bipolar environment2.5, 11.4
Bit-map, essential5.3
Bitblt9.2
Black box1.1
Blending matrix9.2
Block
  transfer (BLT)9.2
  function1.2
Boatload7.3
Body (EDIF)D
Bonding-machine format7.3
Borderpattern (EDIF)D
Boston geometry3.6
Bottom-up
  design1.2
  placement4.3
  programming8.1, 8.4
Boundary (GDS II)C
Bounding box1.2
Box
  black1.1
  bounding1.2
  CIFB
  GDS IIC
Branch-and-bound compaction4.2
Branching factor1.2
Bravo310.4
Breadth-first search8.3
Breshenham
  circle9.2
  line9.2
Bristle Blocks4.5
Broadcast11.5
Buffer, frame9.2
Buried contact2.5
C8.2, 11.1
Cache, display9.2
CAD (computer-aided design)1.1
CADAT11.5
CADDIF7.4
Cadre4.5
CAE (computer-aided engineering)1.1
Caesar3.6, 10.4
Call (CIF)B
Calligraphic display9.2
Caltech Intermediate Format, see format, CIF
Cell1.2
  composition1.2
  database8.4
  differentiation1.2
  EDIFD
  Electric11.2
  generation4.2
  leaf1.2
  library2.5
  overlap1.2
  parameterized1.2, 8.1
  procedural8.4
  root1.2
  standard2.5
Change
  batch11.5
  checkpoint10.4
  commit10.4
  database10.4
  undo3.2
Channel4.3
  routing4.3
  -less gate-array4.2
Character recognition10.4
Checking
  design rule5.3, 11.5
  rule5.1
  transistor-ratio5.4
Checkpoint (see also change)10.4
CIF, see format
Circle
  Breshenham9.2
  EDIFD
  GerberA
Circuit
  asynchronous1.3
  designer2.1
  feedback6.6
  integrated1.1
  -level simulation6.2
  printed1.1, 7.2
  synchronous1.3
  wire-wrap1.1
Clipping9.2
  polygon9.2
  screen9.2
  Sutherland-Cohen9.2, 10.3
Clock
  nonoverlapping1.3
  skew1.3
  two-phase1.3
Closed polygon9.2
Cluster, memory3.2
CMOS2.1, 2.5, 11.4
Cognition, human10.2
Color
  additive space9.3
  EDIFD
  four-color9.3
  inversion9.3
  map9.2
  subtractive space9.3
Command
  completion10.4
  language8.2, 10.1, 10.4
Commit10.4
Compaction4.2
  branch-and-bound4.2
  Electric11.5
  fence4.2
  graph4.2
  one-dimensional4.2
  overconstraint4.2
  simulated annealing4.2
  track4.2
Comparison, network5.2
Compensation4.6
  Electric11.5
  negative4.6
  positive4.6
Compiler, silicon1.1, 4.1, 4.5, 11.5
Complex
  component3.3
  prototype11.2
Component
  active1.4
  complex3.3
  -level environment2.4
  passive1.4
  primitive2.1, 3.3, 11.2
  representation3.5
Composition
  cell1.2
  rule1.4
Computer
  address space1.1
  -aided design1.1
  -aided engineering1.1
Connection rule1.4
Connectivity1.1, 1.4
  representation3.5
Consistency in display/hardcopy9.3
Constraint8.1
  backtracking8.3
  connectivity1.4
  design1.1
  Electric11.3
  fixed-angle11.3
  hierarchical-layout11.3
  linear inequality8.3, 11.3
  loop8.3
  overconstraint4.2, 8.3
  propagation8.3
  relaxation8.3
  representation3.2
  rigidity11.3
  sequencing8.3
  slidable11.3
Contact
  buried2.5
  cut2.5
  layer2.5
Contents (EDIF)D
Control
  point9.2
  rule4.5
Conversion, format7.4
Core, SIGGRAPH9.1
Corner stitching3.6
Correspondence, view1.3
Cosine9.2
Crash recovery10.4
Critical dimensions4.6
Criticalsignal (EDIF)D
Crosshair9.4
Crystal5.5
Cubic curve (Gerber)A
Cursor9.4
Curve
  B-spline9.2
  Bezier9.2
  Breshenham9.2
  circular9.2
  control point9.2
  cubicA
  display9.2
  GerberA
  Hermite9.2
  spline9.2
D-algorithm6.5
Daemon3.2, 8.1
Daisy chain7.2
Database
  cell8.4
  change logging10.4
  conversion7.4
  modification3.2
  nonredundant3.6
Dataflow
  actor2.3
  environment2.3
  firing set2.3
  safe2.3
DD (CIF)7.4, B
Declarative programming8.1, 8.3
Define (EDIF)D
Delay modeling6.5
Depth-first search8.3
Design
  bottom-up1.2
  computer aided (CAD)1.1
  constraint1.1
  EDIFD
  environment1.1, 2.1
  frame7.4
  rule checking5.3
    Electric11.5
    hierarchical5.3
    polygon5.3
    raster5.3
    rule4.5
    syntactic5.3
    template5.3
  SLIC1.1, 2.3
  sticks1.1, 2.3
  top-down1.2
  virtual grid1.1, 2.3
Designer
  circuit2.1
  machine architect2.1
  mask2.1
  VLSI2.1
Device model6.1, 6.2, 6.5
DF (CIF)B
Die7.3
Differentiation, cell1.2
Diffusion
  layer2.5
  line tracing4.2
Dimension
  critical4.6
  two-and-one-half1.5
Dimensionality1.1, 1.5
DIP (dual inline package)2.5
Direct method6.2
Disk representation3.2
Display
  aspect ratio9.3
  bilevel9.2
  caching9.2
  calligraphic9.2
  hardcopy consistency9.3
  information10.1, 10.3
  list9.2
  monochrome9.2
  processor9.2
  raster9.2
  vector9.2
Dithering9.3
Document view (EDIF)D
Dot (EDIF)D
Doubly linked list3.2
DPL8.2, 8.4
DRC, see design rule checking
Drilling format7.2
Drop
  shadow9.2
  -in7.3
DS (CIF)B
Dual inline package (DIP)2.5
Dualization4.3
Dynamic analysis5.1, 6.1
EARL8.3
EBES, see format
Edge flag9.2
EDIF, see format
Editing window10.3
Electric2.5, 3.2, 4.2, 10.4, 11.1
Electrical-rule checking (ERC)5.4
Electron Beam Exposure System, see format, EBES
Electronic Design Interchange Format, see format, EDIF
Element (GDS II)C
EMACS10.4
Embedded language8.1
End
  drawing (EBES)E
  of block (EBES)E
  CIFB
  stripe (EBES)E
Environment2.1
  algorithm level2.3
  artwork2.5, 11.4
  bipolar2.5, 11.4
  component level2.4
  dataflow2.3
  design1.1, 2.1
  Electric11.4
  flowcharting2.3
  GEM11.4
  generic11.4
  instruction-set processor (ISP)2.4, 4.5
  layout level2.5
  MOS2.1, 11.4
  object3.3
  PMS2.2
  pseudolayout2.3
  register transfer2.4
  schematic2.3, 11.4
  space2.1
  state diagram2.3
  sticks2.3
  system level2.2
  temporal logic2.3
  virtual grid2.3
ERC (electrical rule checking)5.4
Escher8.2
ESIM11.5
Essential bit-map5.3
Etching layer4.2
Event6.5
Expert system4.5
Exporting11.2
External (EDIF)D
Fabrication, mask4.6, 7.3
Facet11.2
Fan-in5.4
Fan-out5.4
Feedback
  circuit6.6
  input device9.4
  user10.1, 10.5
Fence4.2
Fiducial marks4.6
Field
  -effect transistor2.5
  gravity10.4
Figuregroup (EDIF)D
Figuregroupdefault (EDIF)D
Filled polygon9.2
Fillpattern (EDIF)D
Firing set2.3
FIRST4.5
Fitt's law10.4
Fixed-angle constraint11.3
Flag
  edge9.2
  marking3.2
Flat1.2
Floating input5.4
Floor
  -plan, screen10.3
  -planning, see placement
Flowcharting2.3
Folding4.2
Font9.2
Footprint1.2
Format
  bonding machine7.3
  CADDIF7.4
  CIF (Caltech Intermediate Format)7.3, 11.5, B
    boxB
    callB
    definition delete (DD)7.4, B
    definition finish (DF)B
    definition start (DS)B
    endB
    layerB
    polygonB
    roundflashB
    user extensionsB
    wireB
  conversion7.4
  disk3.2
  drilling7.2
  EBES (Electron Beam Exposure System)7.3, E
    address unitE
    end drawingE
    end of blockE
    end stripeE
    parallelogramE
    rectangleE
    start drawingE
    start stripeE
    stripeE
    trapezoidE
  EDIF (Electronic Design Interchange Format)7.3, 11.5, D
    annotateD
    arcD
    arraydefinitionD
    arrayrelatedinfoD
    behavior viewD
    bodyD
    borderpatternD
    cellD
    circleD
    colorD
    contentsD
    criticalsignalD
    defineD
    designD
    document viewD
    dotD
    externalD
    figuregroupD
    figuregroupdefaultD
    fillpatternD
    globalD
    gridmapD
    instanceD
    instancemapD
    interfaceD
    joinedD
    libraryD
    logicmodelD
    mask layout viewD
    measuredD
    memberD
    multipleD
    mustjoinD
    netlist viewD
    numberdefinitionD
    orientationD
    pathD
    pathtypeD
    permutableD
    pointD
    polygonD
    portimplementationD
    portmapD
    qualifyD
    rectangleD
    renameD
    requiredD
    rotationD
    scaleD
    scalex/yD
    schematic viewD
    sectionD
    shapeD
    signalgroupD
    simulateD
    statusD
    stepD
    stranger viewD
    symbolic viewD
    technologyD
    timingD
    transformD
    translateD
    unusedD
    viewD
    viewmapD
    weakjoinedD
    widthD
    wireD
    writtenD
  GDS II7.3, 11.5, C
    array referenceC
    boundaryC
    box7.4, C
    elementC
    libraryC
    node7.4, C
    pathC
    structureC
    structure referenceC
    textC
  Gerber7.2, A
    circular arcA
    cubic curveA
    lineA
    parabolic curveA
    penA
    preparatory function codeA
    textA
  integrated circuit7.3
  interchange7.1
  manufacturing7.1
  numerically controlled (NC) drilling7.2
  printed-circuit7.2
  SDIF (Stimulus Data Interchange Format)7.4
  SHIFT7.3
  tester7.4
  wire-wrap7.2
Formatting language8.2
FORTRAN4.5
Foundry
  MOS Implementation Service (MOSIS)7.4
  silicon7.4
Four-color9.3
Frame
  buffer9.2
  design7.4
  pad7.4
Fully instantiated1.2
Function block1.2
Functional
  hierarchical organization1.2
  -level simulation6.4
  verification5.5
Garbage-collection3.2
Gate
  -array4.2
    channel-less4.2
    macro4.2
  -level simulation6.3
  matrix
    generator4.2
    greedy algorithm4.2
GDS II, see format
GEM environment11.4
Generator
  cell4.2
  external to cells4.3
  gate matrix4.2
  postlayout4.6
  programmable logic array4.2, 11.5
  regular forms4.2
  test vector5.1
Geometric design-rule checking5.3, 11.5
Geometry
  algebra3.6
  Boston3.6
  Manhattan3.6
  representation3.6
Gerber, see format
Gestalt9.3
GKS9.1
Global
  EDIFD
  routing4.3
Glyph10.3
GPL8.2
Graph
  compaction4.2
  isomorphism5.2
Graphics9.1
  accelerator9.2
  command language10.4
  mask4.6
  package9.1
  programming8.1
  representation3.6
Gravity field10.4
Greedy algorithm4.2
Grid array2.5
Gridmap (EDIF)D
Hardcopy9.3
Hardware-description language1.1, 8.2
Hash table3.2
Help10.4
Hephaestus4.5
Hermite curve9.2
Heuristic1.1
Hierarchy1.2
  branching factor1.2
  connectivity1.4
  design-rule checking5.3
  functional organization1.2
  layout constraints11.3
  organization1.2
  physical1.3
  representation3.3
  separated1.2
  spatial organization1.2
  structural1.1
  view1.3
Hightower routing4.3
History list3.2
HPGL11.5
Human
  cognition10.2
  engineering10.1
  memory1.2
  motion10.2
  perception10.2
I8.3
IAGL8.2
IC, see integrated circuit
Icarus10.3
Icon10.3
Iconic9.2
ICPL8.2
Idiomatic placement4.3
Imperative programming8.1, 8.2
Implant layer2.5
Implementation service7.4
Incremental-time simulation6.5
Information display10.1, 10.3
Input device9.4
  feedback9.4
  joystick9.4
  knob9.4
  light pen9.4
  mouse9.4
  spark pen9.4
  speech9.4
  tablet9.4
  thumbwheel9.4
  touch screen9.4
  tracker ball9.4
  valuator9.4
Instance1.2
  EDIFD
  node11.2
Instancemap (EDIF)D
Instruction-set processor (ISP)2.4, 4.5
Integrated circuit (IC)1.1
  batch7.3
  boatload7.3
  die7.3
  format7.3
  package2.4, 2.5
  run7.3
  wafer7.3
Integration
  large scale (LSI)2.5
  medium scale (MSI)2.5
  small scale (SSI)2.5
  tool11.5
  ultra large scale (ULSI)2.5
  very large scale (VLSI)2.5
  wafer scale (WSI)2.5
Intensity resolution9.2
Interchange
  electronic design format see format, EDIF
  format7.1
  stimulus data format7.4
Interface
  EDIFD
  user10.1, 11.5
Interference
  acoustic10.2
  semantic10.2
Interval temporal logic2.3
Invisible arc11.4
Isolated-circuit detection5.4
Isomorphism, graph5.2
ISP (instruction-set processor)2.4, 4.5
Jargon10.2
Joined (EDIF)D
Joystick9.4
Junction transistor2.5
Juno3.2, 8.3, 8.4
Knob9.4
L8.2
Lambda3.6, 5.3
Language
  Ada8.2
  ALI8.3
  APL8.2
  BASIC8.2
  C8.2, 11.1
  command8.2, 10.1, 10.4
    graphics10.4
    textual10.4
  EARL8.3
  embedded8.1
  formatting8.2
  FORTRAN4.5
  GPL8.2
  hardware description1.1, 8.2
  I8.3
  IAGL8.2
  ICPL8.2
  L8.2
  LAVA8.3
  LISP7.3, 7.4, 8.2, 11.1, 11.3
  Mathematica11.1, 11.3
  picture8.2
  PL/I8.2
  Plates8.3
  PostScript9.3, 11.5
  Prolog11.3
  SILT8.3
  TCL11.1, 11.3
Large-scale integration (LSI)2.5
LAVA8.3
Layer
  buried2.5
  contact2.5
  CIFB
  diffusion2.5
  etching4.2
  implant2.5
  metal2.5
  native substrate2.5
  overglass2.5
  polysilicon2.5
  via2.5
  well2.5
Layout
  hierarchical constraint11.3
  -level environment2.5
  masklayout view, EDIFD
  pad4.3
Leaf cell1.2
Ledeen character recognizer10.4
Lee-Moore routing4.3
Library
  cell2.5
  EDIFD
  Electric11.2
  GDS IIC
  object3.3
Light pen9.4
Line
  Breshenham9.2
  diffusion tracing4.2
  drawing9.2
  GerberA
Linear-inequality constraint8.3, 11.3
Linked list3.2
  doubly3.2
LISP7.3, 7.4, 8.2, 11.1, 11.3
List
  display9.2
  history3.2
  linked3.2
Locality3.6
Logging user input10.4
Logic
  interval temporal2.3
  -level simulation6.3
  random4.2
  temporal2.3
  uncommitted array4.2
Logicmodel (EDIF)D
Long-term memory10.2
Loose routing4.3
LSI (large-scale integration)2.5
Lyra5.3
Machine
  architect2.1
  simulation6.7
Macro1.2
  gate-array4.2
  package8.2
Manhattan geometry3.6
Manufacturing format7.1
Map
  color9.2
  essential bit5.3
Marching menu10.3
Marking3.2
MARS11.5
Mask
  designer2.1
  fabrication7.3
  graphics4.6
  layout view, EDIFD
  write9.2
Master-slice4.2
Matrix
  blending9.2
  gate4.2
  personality4.2
Maze routing4.3
Measured (EDIF)D
Medium-scale integration (MSI)2.5
Member (EDIF)D
Memory
  allocation3.2
  cluster3.2
  human1.2
  long term10.2
  paging3.2
  read only4.2
  short term10.2
Menu10.3
  marching10.3
  number10.4
  pop-up10.3
  pulldown10.3
Message window10.3
Metal
  layer2.5
  migration5.4
Metal oxide semiconductor, see MOS
Migration, metal5.4
Military standard2.3
Min-cut placement4.3
Miss Manners4.5
Mixed-mode simulation6.4
Mode10.4
Model
  delay6.5
  device6.1, 6.2, 6.5
  task10.1, 10.2
  user10.1, 10.2
Module1.2
Möire pattern9.2
Monochrome display9.2
MOS2.1
  CMOS2.1, 2.5, 11.4
  environment11.4
  nMOS2.1, 2.5, 11.4
MOSIS7.4
MOSSIM11.5
Motion
  human10.2
  pen9.3
Mouse9.4
  optical9.4
MSI (medium-scale integration)2.5
Multidesigner circuits1.2
Multilayer routing4.3
Multilevel simulation6.4
Multiperson project3.3
Multiple
  EDIFD
  -state simulation6.3
  -wire routing4.3
Mustjoin (EDIF)D
Native substrate layer2.5
NC (numerically controlled drilling)7.2
Negative compensation4.6
Net1.4
Netlist1.4
  EDIF viewD
Network1.4
  comparison5.2
  maintenance (Electric)11.5
  resistive4.3
NEWSWHOLE10.5
NMOS2.1, 2.5, 11.4
Node
  Electric11.2
  extraction1.4, 5.2, 6.5
    polygon5.2
    raster5.2
  GDS IIC
  instance11.2
  object3.5
  prototype11.2
Nonoverlapping clock1.3
Nonredundant database3.6
NS8.2, 8.4
Number
  menu10.4
  wheel10.4
  winding3.6
Numberdefinition (EDIF)D
Numerically controlled (NC) drilling format7.2
Object3.2
  arc3.5, 11.2
  environment3.3
  library3.3, 11.2
  marking3.2
  node3.5, 11.2
  port3.5, 11.2
  prototype11.2
  technology11.2, 11.4
  tool11.2
Obstacle4.3
Obstruction4.3
One-dimensional compaction4.2
Opened polygon9.2
Optical
  character recognition10.4
  mouse9.4
Or plane4.2
Orientation
  EDIFD
  restriction3.6
Overconstraint8.3
  compaction4.2
Overglass layer2.5
Overlap, cell1.2
Package
  dual inline (DIP)2.5
  graphics9.1
  integrated circuit2.4, 2.5
  macro8.2
  pin grid array2.5
  polygon3.6
  quad2.5
  single inline (SIP)2.5
Packaging7.3
Pad
  frame7.4
  layout4.3
Paging memory3.2
Painting1.4
Palladio8.3
Parabolic curve (Gerber)A
Parallelogram (EBES)E
Parameterized cell1.2, 8.1
Parity scan9.2
Passive component1.4
Path
  EDIFD
  GDS IIC
Pathtype (EDIF)D
Pattern
  artwork4.6
  fill9.3
  möire9.2
PC (printed circuit)1.1, 7.2
Pen
  light9.4
  motion9.3
  spark9.4
  writing (Gerber)A
Perception, human10.2
Permutable (EDIF)D
Personality matrix4.2
PHIGS9.1
Photoplotter7.2
Physical hierarchy1.3
PI4.3
Picture language8.2
Pin
  grid array2.5
  wire-wrap7.2
Pitch matching4.4
Pixel9.2
PL/I8.2
PLA, see programmable logic array
Placement4.3
  and routing4.3
  bottom-up4.3
  dualization4.3
  idiomatic4.3
  min-cut4.3
  resistive network4.3
  simulated annealing4.3
Plates8.3
PMS environment2.2
Point (EDIF)D
Polygon
  CIFB
  clipping9.2
  closed9.2
  design-rule checking5.3
  drawing9.2
  edge flag9.2
  EDIFD
  filling9.2
  node extraction5.2, 6.5
  opened9.2
  package3.6
  parity scan9.2
  pattern fill9.3
  seed fill9.2
Polysilicon layer2.5
Pop-up menu10.3
Port
  Electric11.2
  object3.5
Portimplementation (EDIF)D
Portmap (EDIF)D
Positive compensation4.6
Postlayout generation4.6
PostScript9.3, 11.5
Power estimation5.4, 6.5
Preparatory function code (Gerber)A
Primitive
  component2.1, 3.3
  prototype11.2
Printed circuit (PC)1.1
  format7.2
Procedural cell8.4
Process technology, semiconductor1.1, 2.1
Processor, display9.2
Programmable logic array
  and plane4.2
  Electric11.5
  folding4.2
  generation4.2
  or plane4.2
  personality matrix4.2
  splitting4.2
Programming8.1
  adding8.1
  bottom-up8.1, 8.4
  declarative8.1, 8.3
  Electric11.3
  graphics8.1
  imperative8.1, 8.2
  textual8.1
  top-down8.1, 8.4
Project, multiperson3.3
Prolog11.3
Propagation, constraint8.3
Prototype3.2
  complex11.2
  object11.2
  node11.2
  primitive11.2
Pseudolayout environments2.3
Puck9.4
Pulldown menu10.3
Quad
  package2.5
  tree representation3.6
Qualify (EDIF)D
QuickDraw11.5
R-tree representation3.6, 11.2
Race condition1.3
Rand tablet9.4
Random logic4.2
Raster
  design-rule checking5.3
  display9.2
  node extraction5.2
  scan5.2
Ratio
  aspect9.3
  checking5.4
RC tree5.5, 6.5
Read-only memory (ROM)4.2
Recovery, crash10.4
Rectangle
  EBESE
  EDIFD
Register transfer2.4
Regular form generation4.2
Relation
  a-kind-of3.4
  a-part-of3.4
  an-instance-of3.4
Relaxation
  constraint8.3
  techniques6.2
Rename (EDIF)D
Representation3.1
  component3.5
  connectivity3.5
  corner stitching3.6
  disk3.2
  Electric11.2
  essential bit-map5.3
  geometry3.6
  graphics3.6
  hierarchy3.3
  quad-tree3.6
  R-tree3.6, 11.2
  shape3.6
  tree3.6
  view3.4
  winged-edge3.6
  wire3.5
Required (EDIF)D
Resistive network placement4.3
Resolution
  intensity9.2
  spatial9.2
Restored signal5.4
Rigidity constraint11.3
River routing4.3
RNL11.5
ROM (read-only memory)4.2
Root cell1.2
Rotation (EDIF)D
Roto-routing4.3
Roundflash (CIF)B
Routing4.3
  backtracking4.3
  channel4.3
  Electric11.5
  global4.3
  Hightower4.3
  Lee-Moore4.3
  loose4.3
  maze4.3
  multilayer4.3
  multiple wire4.3
  obstacle4.3
  obstruction4.3
  river4.3
  roto4.3
  simulated annealing4.3
  switchbox4.3
RSIM6.5, 11.5
Rule (see also design rule)
  checking5.1
    design5.3, 11.5
    electrical5.4
  composition1.4
  connection1.4
  control4.5
  design4.5, 5.3
Run, integrated circuit7.3
Safety2.3
SAM8.2
Sawing4.6
Scale (EDIF)D
Schematic
  capture2.3
  EDIF viewD
  environment2.3, 11.4
Screen clipping9.2
Scribe lane4.6
Scribing4.6
Scroll-bar10.3
Scrolling10.3
SDIF (Stimulus Data Interchange Format)7.4
Search
  breadth-first8.3
  depth-first8.3
  spatial3.6
Section1.2
  EDIFD
Seed fill9.2
Semantic interference10.2
Semiconductor process technology1.1, 2.1
Sequencing, constraints8.3
Separated hierarchy1.2
Shape
  EDIFD
  representation3.6
Sheet3.6
SHIELD6.2
SHIFT7.3
Short
  circuit detection5.4
  term memory10.2
SIGGRAPH Core9.1
Signal
  restored5.4
  unrestored5.4
Signalgroup (EDIF)D
Silicon
  compiler1.1, 4.1, 4.5, 11.5
  foundry7.4
SILT8.3
Simulate (EDIF)D
Simulated annealing
  compaction4.2
  placement4.3
  routing4.3
Simulation5.1, 6.1
  behavioral level6.4
  circuit level6.2
  Electric11.5
  event6.5
  functional level6.4
  gate level6.3
  incremental time6.5
  logic level6.3
  machines6.7
  mixed mode6.4
  multilevel6.4
  multiple state6.3
  switch level6.3
  timing6.5
Sine9.2
Single inline package (SIP)2.5
Sketchpad3.2, 8.3
Skew, clock1.3
SLIC design1.1, 2.3
Slice, master4.2
Slidable constraint11.3
Small-scale integration (SSI)2.5
Socket7.2
Space
  color9.3
  computer address1.1
  environment2.1
Spark pen9.4
Spatial
  dimensionality1.5
  hierarchical organization1.2
  resolution9.2
  search3.6
Speech input9.4
SPICE5.5, 7.4, 11.5
Spline curve9.2
Splitting4.2
SSI (small-scale integration)2.5
Standard cell2.5
Start
  drawing (EBES)E
  stripe (EBES)E
State diagram2.3
Static analysis5.1
Status (EDIF)D
Step (EDIF)D
Sticks
  design1.1
  environment2.3
Stimulus Data Interchange Format (SDIF)7.4
Storage/logic array4.2
Stranger view (EDIF)D
Stripe (EBES)E
Structure
  GDS IIC
  hierarchy1.1
  reference, GDS IIC
Substrate layer2.5
Subtractive color space9.3
Sutherland-Cohen clipping9.2, 10.3
Switch-level simulation6.3
Switchbox4.3
  routing4.3
Symbolic view (EDIF)D
Synchronous circuit1.3
Syntactic design-rule checking5.3
Synthesis1.1, 4.1
  cell generation4.2
  diffusion-line tracing4.2
  expert system4.5
  gate matrix4.2
  gate-array4.2
  pad layout4.3
  placement4.3
  placement and routing4.3
  programmable-logic-array generation4.2, 11.5
  routing4.3, 11.5
  silicon compiler1.1, 4.1, 4.5, 11.5
  storage/logic array4.2
  tool1.1, 4.1
  Weinberger array4.2
System
  Bravo310.4
  Bristle Blocks4.5
  Cadre4.5
  Caesar3.6, 10.4
  DPL8.2, 8.4
  editing
    EMACS10.4
  Electric2.5, 3.2, 4.2, 10.4, 11.1
  Escher8.2
  expert4.5
  FIRST4.5
  Hephaestus4.5
  Icarus10.3
  Juno3.2, 8.3, 8.4
  -level environment2.2
  Miss Manners4.5
  NEWSWHOLE10.5
  NS8.2, 8.4
  operating
    TENEX10.4
    UNIX10.4
  Palladio8.3
  Polygon package3.6
  SAM8.2
  Sketchpad3.2, 8.3
  Talib4.5
  ThingLab3.2, 8.3
  Vexed4.5
Table, hash3.2
Tablet9.4
  puck9.4
  Rand9.4
  spark pen9.4
Talib4.5
Target, artwork4.6
Task model10.1, 10.2
Technology
  EDIFD
  Electric11.4
  object11.2, 11.4
  semiconductor process1.1, 2.1
Template, design-rule checking5.3
Temporal1.3
  logic2.3
  interval2.3
TENEX10.4
Terminology10.2
Test
  format7.4
  inputs6.5
  vector5.1, 6.1
Text
  command language10.4
  drawing9.2
  GDS IIC
  GerberA
  programming8.1
  window10.3
ThingLab3.2, 8.3
Through hole7.2
Thumbwheel9.4
Tied outputs5.4
Time6.1, 6.5
  stamp3.2
Timed acceleration9.4
Timing
  EDIFD
  simulation6.5
  verification5.5
Tool
  analysis1.1, 4.1
  CADAT11.5
  Crystal5.5
  Electric11.5
  ESIM11.5
  integration11.5
  Lyra5.3
  MARS11.5
  MOSSIM11.5
  object11.2
  PI4.3
  RNL11.5
  RSIM6.5, 11.5
  SHIELD6.2
  SPICE5.5, 7.4, 11.5
  synthesis1.1, 4.1
  Tpack4.2, 8.2
  TV5.5
Top-down
  design1.2
  programming8.1, 8.4
Topology1.1, 1.3
Touch screen9.4
Tpack4.2, 8.2
Track4.2
Tracker ball9.4
Transform (EDIF)D
Transformation3.6, 9.2
Transistor
  field effect2.5
  junction2.5
  ratio checking5.4
Translate (EDIF)D
Trapezoid (EBES)E
Traveling-salesman4.3
Tree
  quad3.6
  R3.6
  RC5.5, 6.5
  representation3.6
Turn11.5
TV5.5
Twisted-pair7.2
Two-and-one-half-dimensional1.5
Two-phase clock1.3
Typeface9.2
Ultra-large-scale integration (ULSI)2.5
Uncommitted logic array4.2
Undo3.2
Universal arc11.4
UNIX10.4
Unrestored signal5.4
Unrouted arc11.4
Unused (EDIF)D
User
  extension (CIF)B
  input logging10.4
  interface10.1, 11.5
  model10.1, 10.2
Valuator9.4
Vector
  display9.2
  test5.1, 6.1, 6.5
Verification5.1, 5.5
  functional5.5
  timing5.5
Very-large-scale integration (VLSI)1.1, 2.5
Vexed4.5
Via layer2.5
View1.1, 1.3
  behavior1.3
  correspondence1.3
  EDIFD
  hierarchy1.3
  representation3.4
  temporal1.3
  topology1.3
Viewmap (EDIF)D
Virtual grid
  design1.1
  environment2.3
VLSI
  chips1.1
  designer2.1
Wafer
  cutting4.6
  integrated circuit7.3
  scale integration2.5
Weakjoined (EDIF)D
Weinberger array4.2
Well layer2.5
Wheel
  number10.4
  thumb9.4
Width (EDIF)D
Winding number3.6
Window
  editing10.3
  message10.3
Winged-edge representation3.6
Wire
  CIFB
  EDIFD
  invisible11.4
  representation3.5
  universal11.4
Wire-wrap1.1
  format7.2
  pin7.2
  socket7.2
Wired-and1.4
Wired-or1.4
Write mask9.2
Written (EDIF)D
WSI (wafer-scale integration)2.5
Yorktown simulation engine6.7


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Steven M. Rubin
    Static Free Software