Preparing the simulation

This lesson will use an example design that contains lower level VHDL blocks in the files control.vhd, retrieve.vhd, and store.vhd; and top level block, test bench and configuration files - ringrtl.vhd, testring.vhd, and config_rtl.vhd.

1. Start by creating a new working directory, making it the current directory, and copying the files from \modeltech\examples\profiler into it.


2. Use the vlib command to create a work library in the current directory.



vlib work 

(MENU: Design > Create a New Library)

3. Use the vmap command to map the work library to a physical directory. A modelsim.ini file will be written into the work directory.



vmap work work 

4. Compile the lower level blocks of the design.



vcom control.vhd retrieve.vhd store.vhd 

  


  (MENU: Design > Compile)
  

5. Compile the top level block, test bench and configuration files.



vcom ringrtl.vhd testring.vhd config_rtl.vhd 

  


  (MENU: Design > Compile)
  

6. Use the vsim command to load the design configuration.



vsim work.test_bench_rtl 

  


  (MENU: Design > Load Design)
  

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