Vector ports

The entities generated by sm_entity only contain single-bit ports, never vectored ports. This is necessary because ModelSim correlates entity ports with the SmartModel SWIFT interface by name. However, for ease of use in component instantiations, you may want to create a custom component declaration and component specification that groups ports into vectors. You can also rename and reorder the ports in the component declaration. You can also reorder the ports in the entity declaration, but you can't rename them!

The following is an example component declaration and specification that groups the address and data ports of the CY7C285 SmartModel:

component cy7c285
	generic ( TimingVersion : STRING := "CY7C285-65";
		DelayRange : STRING := "Max";
		MemoryFile : STRING := "memory" );
	port ( A : in std_logic_vector (15 downto 0);
		CS : in std_logic;
		O : out std_logic_vector (7 downto 0);
		WAIT_PORT : inout std_logic );
end component;
 
for all: cy7c285
	use entity work.cy7c285
	port map (A0 => A(0),
		A1 => A(1),
		A2 => A(2),
		A3 => A(3),
		A4 => A(4),
		A5 => A(5),
		A6 => A(6),
		A7 => A(7),
		A8 => A(8),
		A9 => A(9),
		A10 => A(10),
		A11 => A(11),
		A12 => A(12),
		A13 => A(13),
		A14 => A(14),
		A15 => A(15),
		CS => CS,
		O0 => O(0),
		O1 => O(1),
		O2 => O(2),
		O3 => O(3),
		O4 => O(4),
		O5 => O(5),
		O6 => O(6),
		O7 => O(7),
		WAIT_PORT => WAIT_PORT ); 

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