Invoking the VHDL compiler

ModelSim compiles one or more VHDL design units with a single invocation of vcom, the VHDL compiler. The design units are compiled in the order that they appear on the command line. For VHDL, the order of compilation is important - you must compile any entities or configurations before an architecture that references them.

You can simulate a design containing units written with both the 1076 1987 and 1076 1993 versions of VHDL. To do so you will need to compile units from each VHDL version separately. The vcom command compiles units written with version 1076 1987 by default; use the 93 option with vcom to compile units written with version 1076 1993. You can also change the default by modifying the modelsim.ini file (see "Preference variables located in INI files" for more information).

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