Value Change Dump (VCD) Files

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Chapter contents

ModelSim VCD commands and VCD tasks

Creating a VCD file

Flow for four-state VCD file

Flow for extended VCD file

Resimulating a design from a VCD file

Example 1 - Verilog counter

Example 2 - VHDL adder

Example 3 - Mixed-HDL design

A VCD file from source to output

VHDL source code

VCD simulator commands

VCD output

Capturing port driver data

Supported TSSI states

Strength values

Port identifier code

Example VCD output from vcd dumpports

This chapter explains Model Technology's Verilog VCD implementation for ModelSim.

The VCD file format is specified in the IEEE 1364 standard. It is an ASCII file containing header information, variable definitions, and variable value changes. VCD is in common use for Verilog designs, and is controlled by VCD system task calls in the Verilog source code. ModelSim provides simulator command equivalents for these system tasks and extends VCD support to VHDL designs; the ModelSim commands can be used on either VHDL or Verilog designs.

Note: If you need vendor-specific ASIC design-flow documentation that incorporates VCD, please contact your ASIC vendor.

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