[lmc] Logic Modeling variables
Logic Modeling SmartModels and hardware modeler interface
ModelSim's interface with Logic Modeling's SmartModels and hardware modeler are specified in the [lmc] section of the INI/MPF file; for more information see "VHDL SmartModel interface" and "VHDL Hardware Model interface" respectively.
Spaces in path names
For the Src_Files and Work_Libs variables, each element in the list is enclosed within curly braces ({}). This allows spaces inside elements (since Windows allows spaces inside path names). For example a source file list might look like:
Src_Files = {$MODELSIM_PROJECT/counter.v} {$MODELSIM_PROJECT/tb counter.v}Where the file tb counter.v contains a space character between the "b" and "c".
Model Technology Incorporated Voice: (503) 641-1340 Fax: (503)526-5410 www.model.com sales@model.com |