Naming fields in VHDL signals

Fields in VHDL record signals can be specified using the form:

signal_name.field_name 

Example pathnames

Syntax	Description
clk	specifies the item clk in the current environment
/top/clk	specifies the item clk in the top-level design unit.
/top/block1/u2/clk	specifies the item clk, two levels down from the top-level design unit
block1/u2/clk	specifies the item clk, two levels down from the current environment
array_sig(4)	specifies an index of an array item
{array_sig(1 to 10)}	specifies a slice of an array item in VHDL syntax
{mysignal[31:0]}	specifies a slice of an array item in Verilog syntax
record_sig.field	specifies a field of a record

Model Technology Incorporated Voice: (503) 641-1340 Fax: (503)526-5410 www.model.com sales@model.com