While Loop
A while loop is another form of sequential loop statement that specifies the conditions under which the loop should continue, rather than specifying a discrete number of iterations. The general form of the while loop is shown below:
architecture while_loop of my_entity is
begin
. . .
process(. . .)
begin
. . .
loop_name: while (condition) loop
-- repeated statements go here
end loop loop_name;
. . .
end process;
. . .
end while_loop;
Like the for loop, a while loop can only be entered and used in sequential VHDL statements (i.e., in a process, function or procedure). The loop name is optional.
The following example uses a while loop to describe a constantly running clock that might be used in a test bench. The loop causes the clock signal to toggle with each loop iteration, and the loop condition will cause the loop to terminate if either of two flags (error_flag or done) are asserted.
process
begin
while error_flag /= ‘1’ and done /= '1’ loop
Clock <= not Clock;
wait for CLK_PERIOD/2;
end loop;
end process;
Note: Although while loops are quite useful in test benches and simulation models, you may have trouble if you attempt to synthesize them. Synthesis tools may be unable to generate a hardware representation for a while loop, particularly if the loop expression depends on non-static elements such as signals and variables. Because support for while loops varies widely among synthesis tools, we recommend that you not use them in synthesizable design descriptions.
See also
