-----------------------------------------------------------
-- Memory Controller  (FLEX10k)
-- < memctrl.vhd >
-- 1999/01/21 (Thu) 
-- yamaoka@tube.ee.uec.ac.jp
------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library metamor;
use metamor.attributes.all;

entity memctrl is
port (  CLK  : in std_logic;                    
        RESET : in std_logic;
		ADRS : out std_logic_vector(16 downto 0);      
        ADRS_BUF : in std_logic_vector(16 downto 0);  
		DATA : inout std_logic_vector(31 downto 0);
        WR_DATA : in std_logic_vector(31 downto 0); 
		RD_DATA : out std_logic_vector(31 downto 0);
		SCS  : out std_logic_vector(3 downto 0);  
        SOE  : out std_logic; 
        SWE  : out std_logic; 
		MEM_STATE_SEL : in std_logic_vector(1 downto 0); 
		WR_CYCLE : out std_logic; 
		RD_CYCLE : out std_logic 
);
end memctrl;
architecture RTL of memctrl is  

type MEM_STATE_TYPE is ( 
  STOP, WRITE1, WRITE2,
  READ1, READ2, CONT_READ 
  );

signal CURRENT_STATE : MEM_STATE_TYPE;
signal NEXT_STATE : MEM_STATE_TYPE; 
signal NEXT_MEM_CYCLE : std_logic;
signal OE  : std_logic; 
signal DATA_BUF  : std_logic_vector(31 downto 0); 

constant WRITE_CYCLE     : std_logic_vector(1 downto 0) := "00";
constant READ_CYCLE      : std_logic_vector(1 downto 0) := "01";
constant CONT_READ_CYCLE : std_logic_vector(1 downto 0) := "10";

begin

DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when OE = '1' else DATA_BUF;

process ( RESET, CLK ) begin
if RESET = '1' then
	SOE <= '1';
	SWE <= '1';
	SCS <= "1111";
	OE <= '1';
	ADRS <= ( others => '0' );
	DATA_BUF <= ( others => '0' );
	RD_DATA <= ( others => '0' );
	WR_CYCLE <= '0'; 
	RD_CYCLE <= '0';
	NEXT_MEM_CYCLE <= '0';
	NEXT_STATE <= STOP;
elsif rising_edge( CLK ) then

case CURRENT_STATE is

    when STOP =>
        SOE <= '1';
        SWE <= '1';
        SCS <= "1111";
        OE <= '1';         
		WR_CYCLE <= '0';
		RD_CYCLE <= '0';
		NEXT_MEM_CYCLE <= '0';

    when WRITE1 =>
        SCS <= "0000";
        ADRS <= ADRS_BUF;   
		DATA_BUF <= WR_DATA;
        OE <= '0';
		NEXT_MEM_CYCLE <= '1';
		NEXT_STATE <= WRITE2;
        		        
    when WRITE2 =>
        SWE <= '0';
        WR_CYCLE <= '1';
		NEXT_STATE <= STOP;
        		
    when READ1 => 
        SCS <= "0000";
        SOE <= '0'; 
        ADRS <= ADRS_BUF;   
		NEXT_MEM_CYCLE <= '1';
		NEXT_STATE <= READ2; 
        
    when READ2 =>
        RD_DATA <= DATA;
		RD_CYCLE <= '1';   
		NEXT_STATE <= STOP;
	        
    when CONT_READ =>
		SOE  <= '0';
		SWE  <= '1';
		SCS  <= "0000";
		OE   <= '1';
		ADRS <= ADRS_BUF;
	
	when others => 
		NEXT_STATE <= STOP;  

end case;
end if;
end process;


process ( RESET, CLK ) begin
if RESET = '1' then
	CURRENT_STATE <= STOP;
elsif falling_edge( CLK ) then
	if NEXT_MEM_CYCLE = '0' then 
		case MEM_STATE_SEL is
			when WRITE_CYCLE =>
				CURRENT_STATE <= WRITE1;
			when READ_CYCLE =>
				CURRENT_STATE <= READ1;		
			when CONT_READ_CYCLE =>
				CURRENT_STATE <= CONT_READ;
			when others =>
				CURRENT_STATE <= STOP;
		end case;
 	else 
 		CURRENT_STATE <= NEXT_STATE;
	end if;
end if;
end process;
end RTL;