------------------------------------------------------------
-- Floating Point Number Adder  (FLEX10k)
-- < fpadd.vhd >
-- 1998/11/17 (Tue) 
-- yamaoka@tube.ee.uec.ac.jp
------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity fpadd is
  port ( CLK  : in std_logic;                    
         FA   : in std_logic_vector(31 downto 0); 
         FB   : in std_logic_vector(31 downto 0);  
         Q    : out std_logic_vector(31 downto 0)    
      );

end fpadd;
architecture RTL of fpadd is

signal INF1, INF2, INF3, ZA1, ZA2, ZA3, ZB1, ZB2, ZB3 : std_logic;
signal SA1, SA2, SA3, SB1, SB2, SB3                   : std_logic;
signal EA1, EA2, EB1, EB2                             : std_logic_vector(8 downto 0);
signal EA3, EA4, EQ, ED1, ED2                         : std_logic_vector(7 downto 0);
signal MA1, MA2, MA3, MB1, MB2, MB5                   : std_logic_vector(22 downto 0); 
signal MB3                                            : std_logic_vector(23 downto 0); 
signal MA4, MB4                                       : std_logic_vector(25 downto 0); 
signal MQ1, MQ2                                       : std_logic_vector(25 downto 0);
signal MQ3, MQ4                                       : std_logic_vector(24 downto 0);
signal MQ5                                            : std_logic_vector(22 downto 0);
signal V0, V1, V2, V3, V4, V5                         : std_logic_vector(24 downto 0);
signal VV0, VV1, VV2, VV3, VV4                        : std_logic_vector(24 downto 0);
signal VES1, VES2                                     : std_logic_vector(8 downto 0);

begin

INF1 <= '1' when FA(30 downto 23) = "11111111" or FB(30 downto 23) = "11111111" else '0';
ZA1 <= '1' when FA(30 downto 23) = "00000000" else '0';
ZB1 <= '1' when FB(30 downto 23) = "00000000" else '0';

EA1 <= '0' & FA(30 downto 23);
EB1 <= '0' & FB(30 downto 23);

process begin
wait until rising_edge( CLK );
	SA1 <= FA(31);
	SB1 <= FB(31);
	EA2 <= EA1;
	EB2 <= EB1;
	MA1 <= FA(22 downto 0);
	MB1 <= FB(22 downto 0);
	INF2 <= INF1;
	ZA2 <= ZA1;
	ZB2 <= ZB1;
end process;

VES1 <= EA2 - EB2;
VES2 <= EB2 - EA2; 

SA2 <= SA1 when VES1(8) = '0' else SB1;
SB2 <= SB1 when VES1(8) = '0' else SA1;

EA3 <= EA2(7 downto 0) when VES1(8) = '0' else EB2(7 downto 0);
ED1 <= VES1(7 downto 0) when VES1(8) = '0' else VES2(7 downto 0);

MA2 <= MA1 when VES1(8) = '0' else MB1;
MB2 <= MB1 when VES1(8) = '0' else MA1;

ZA3 <= ZA2 when VES1(8) = '0' else ZB2;
ZB3 <= ZB2 when VES1(8) = '0' else ZA2;

V0 <= "1" & MB2 & "0" when ED1(0) = '0' else "01" & MB2(22 downto 1) & "0";
V1 <= V0 when ED1(1) = '0' else "00" & V0(24 downto 2);
V2 <= V1 when ED1(2) = '0' else "0000" & V1(24 downto 4);
V3 <= V2 when ED1(3) = '0' else "00000000" & V2(24 downto 8);
V4 <= V3 when ED1(4) = '0' else "0000000000000000" & V3(24 downto 16);
V5 <= V4 + "0000000000000000000000001";
MB3 <= V5(24 downto 1) when ED1(7 downto 5) = "000" else "000000000000000000000000";

MA4 <= "00000000000000000000000000" when ZA3 = '1' else
       "001" & MA2 when SA2 = '0' else
       "00000000000000000000000000" - ("001" & MA2);

MB4 <= "00000000000000000000000000" when ZB3 = '1' else
       "00" & MB3 when SB2 = '0' else
       "00000000000000000000000000" - ("00" & MB3);

MQ1 <= MA4 + MB4;

process begin
wait until rising_edge( CLK );
	EA4 <= EA3;
	MQ2 <= MQ1;
	INF3 <= INF2;
end process;

MQ3 <= MQ2(24 downto 0) when MQ2(25) = '0' else
       "0000000000000000000000000" - MQ2(24 downto 0);

MQ4 <= MQ3 + "0000000000000000000000001";
 
ED2 <=  "00000000" when MQ3(24) = '1' else
        "00000001" when MQ3(23) = '1' else
        "00000010" when MQ3(22) = '1' else 
        "00000011" when MQ3(21) = '1' else
        "00000100" when MQ3(20) = '1' else
        "00000101" when MQ3(19) = '1' else
        "00000110" when MQ3(18) = '1' else
        "00000111" when MQ3(17) = '1' else
        "00001000" when MQ3(16) = '1' else
        "00001001" when MQ3(15) = '1' else
        "00001010" when MQ3(14) = '1' else     
        "00001011" when MQ3(13) = '1' else
        "00001100" when MQ3(12) = '1' else
        "00001101" when MQ3(11) = '1' else
        "00001110" when MQ3(10) = '1' else
        "00001111" when MQ3( 9) = '1' else
        "00010000" when MQ3( 8) = '1' else
        "00010001" when MQ3( 7) = '1' else 
        "00010010" when MQ3( 6) = '1' else  
        "00010011" when MQ3( 5) = '1' else  
        "00010100" when MQ3( 4) = '1' else   
        "00010101" when MQ3( 3) = '1' else  
        "00010110" when MQ3( 2) = '1' else            
        "00010111" when MQ3( 1) = '1' else
        "00011000" when MQ3( 0) = '1' else  
        "10000000";

VV0 <= MQ3 when ED2(0) = '0' else MQ3(23 downto 0) & "0"; 
VV1 <= VV0 when ED2(1) = '0' else VV0(22 downto 0) & "00"; 
VV2 <= VV1 when ED2(2) = '0' else VV1(20 downto 0) & "0000"; 
VV3 <= VV2 when ED2(3) = '0' else VV2(16 downto 0) & "00000000"; 
VV4 <= VV3 when ED2(4) = '0' else VV3( 8 downto 0) & "0000000000000000";
MQ5 <= VV4(23 downto 1) when MQ4(24) = '0' else MQ4(23 downto 1);

EQ <= "11111111" when INF3 = '1' else
      EA4 - ED2 + "00000001" when ED2(7) = '0' else
      "00000000"; 

Q <= MQ2(25) & EQ & MQ5;
end RTL;