6809 Flex Computer Project
Last Updated 15 March 2002
This is the basic HD6309 CPU section as per the SBC09CPU design, with
a few minor
modifications for the I/O processor interface. I have used an 8MHz clock
instead of 12MHz.
the HD6309 uses a Xilinx XC95108 CPLD to handle address decoding, bus
arbitratiion and
Address translation RAM. I've done away with the Floppy disk controller,
the Z8530 SCC,
the 6522 VIA and the MC146818A Real time clock. This has all be replaced
with a MC68HC811E2
I/O co-processor. (see below). The HD6309 still has 4 sockets for RAM,
Flash Memory
and EPROM. It could possible be reduced to 3 or even 2 sockets if board
space becomes a problem.
This is an I/O processor based on the MC68HC811E2 chip with 2Kbytes of
EEPROM
on chip and an external 512Kbyte Static RAM. The RAM is paged in the
bottom 32Kbytes
via port bits [PA0..PA2]. The top 32Kbytes of RAM is fixed to the top
of the 512Kbyte RAM.
This configuration was proposed by Frank Wilson, who has done a lot of
work on the 68HC811
running Flex 2. My thanks go to him for his advice.
The I/O processor talks to the HD6309 via a 1Kbyte Cypress Dual Port Memory
(CY7C130-55PC)
Writing to a particular memory location will cause an interrupt in the
other processor.
I have used Non Maskable Interrupts on the Dual Port RAM in both CPUs.
The MC68HC811E2 has a UART with 5V charge pump interface (MAX232).
It also has an SPI interface to talk to a calendar clock (CDP68HC68T1).
I've put a 16 pin header for interfaceing to the 4 input ADC and 2 I/O
bits on Port A.
I've done away with the IDE interface as there is not enough room on the
PCB for it.
For my SS30 IDE disk interface project go to
http://members.optushome.com.au/jekent/ss30ide
This is the PCB circuit board layout. So far I have just layed out the components.
I have used the free expressPCB software to layout the boar as recommended
by Michael Holley from the FUFU list. You can down load the software from:
http://www.expresspcb.com/
Notes and Ramblings on the Design: