IOE Delays

Table of Contents

PPT Slide

PPT Slide

IOE Delays

Aside: Why programmable Output slew?

GND Bounce

Altera Logic Element

PPT Slide

Minimum Pin To Pin Delay

Minimum Pin To Pin Delay

Minimum Register to Register

Minimum Register to Register

Dedicated Inputs/Clock Pins vs IOE inputs

Setup Time for Logic Element

Clock To Out

Clock To Out

Latching in IOE or LE?

Minimum External Setup Time Data latched in LE

Minimum External Setup Time Data latched in IOE

Chip To Chip

PLL effects

Email: reese@erc.msstate.edu

Home Page: http://www.erc.msstate.edu/~reese

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