VHDL for control

entity control is

port ( clk,reset: in std_logic;

d7_i: in std_logic;

d11_i: in std_logic;

d2312_i: in std_logic;

ra: in std_logic;

rb: in std_logic;

eq: in std_logic;

sp: out std_logic;

roll: out std_logic;

win : out std_logic;

lose: out std_logic;

q0 : out std_logic;

q1 : out std_logic;

q4 : out std_logic;

q5 : out std_logic

);

end control;

Used one-hot encoding. Outputs q0, q1, lose, win,q4, q5 correspond to states S0, S1, S2, S3, S4, S5.

The one hot equations were written by inspection. The VHDL file contains boolean equations for DFF inputs and ra,rb, eq,sp outputs.