A Brief Introduction to Verilog

The following paragraphs give a brief technical introduction to Verilog suitable for the reader with no prior knowledge of the language.

Background

The Verilog Hardware Description Language (HDL) is a language for describing the behaviour and structure of electronic circuits, and is an IEEE standard (IEEE Std. 1364-1995).

Verilog is used to simulate the functionality of digital electronic circuits at levels of abstraction ranging from stochastic and pure behaviour down to gate and switch level, and is also used to synthesize (i.e. automatically generate) gate level descriptions from more abstract (Register Transfer Level) descriptions. Verilog is commonly used to support the high level design (or language based design) process, in which an electronic design is verified by means of thorough simulation at a high level of abstraction before proceeding to detailed design using automatic synthesis tools. Verilog is also widely used for gate level verification of ICs, including simulation, fault simulation and timing verification.

The Verilog HDL was originally developed with the Verilog-XL simulator by Gateway Design Automation, and intoduced in 1984. In 1989 Cadence Design Systems acquired Gateway, and with it the rights to the Verilog language and the Verilog-XL simulator. In 1990 Cadence placed the Verilog language only into the public domain. A non profit making organisation, Open Verilog International (OVI) was formed with the task of taking the language through the IEEE standardization procedure, and Verilog became an IEEE standard in 1995. OVI will continue to maintain and develop the language.

The Language

In this section as in the rest of the guide, words given in capitalised italics are technical terms whose definitions may be found in the main body of this guide.

An hierarchical portion of a hardware design is described in Verilog by a Module. The Module defines both the interface to the block of hardware (i.e. the inputs and outputs) and its internal structure or behaviour.

A number of Gates representing basic logic gates (e.g. and, or) are built into the Verilog language. In addition User Defined Primitives (UDPs) may be defined and used.

The structure of an electronic circuit is described by making Instances of Modules and Primitives within a higher level Module, and connecting the Instances together using Nets. A Net represents an electrical connection, a wire or a bus. A Port Connection List is used to connect Nets to the Ports of a Module or Primitive Instance, where a Port represents a pin. Registers (see below) may also be connected to the input Ports (only) of a Module or Primitive Instance.

Nets (and Registers) have values formed from the logic values 0, 1, X (unknown or uninitialised) and Z (high impedence or floating). In addition to logic values, Nets also have a logic strength.

The behaviour of an electronic circuit is described using Initial and Always statements and Continuous Assignments. Along with Primitives, these represent the leaves in the hierarchy tree of the design. Each Initial, Always, Continuous Assignment and Primitive Instance executes concurrently with respect to all others, but the Statements inside an Initial or Always are in many ways similar to the statements in a software programming language, but are executed at times dictated by timing controls, such as delays, and (simulation) event controls. They execute in sequence in a Begin-end block, or in parallel in a Fork-join block. A Continuous Assignment is a statement which modifies the values of Nets. An Initial or Always statement modifies the values of Registers. An Initial or Always statement can be decomposed into named Tasks and Functions, which can be given parameters. There are also a number of built in System Tasks and Functions. The Programming Language Interface (PLI) is an integral part of the Verilog language, and provides a means of calling functions written in C in the same way as System Tasks and Functions.

Compilation

Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation immediately follows compilation with no data files being created.

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