VHDL FAQ
VHDL FAQ This list of FAQs and any mention of specific organizations or their products does not imply an endorsement by Doulos of either the organisation or the product.
If you would like us to add your FAQ to this list, please e-mail us with the URL of your VHDL-related FAQ and we will include it.
The Doulos VHDL FAQ What is the difference between VHDL and Verilog?
On the surface, not that much. Both are IEEE standards and are
supported by all the major EDA vendors. Both can be used for
designing ASICs and simulating systems. However, VHDL is
altogether a grander language. Its support for system level
modeling and simulation is far more comprehensive than Verilog.
However, VHDL requires longer to learn and is not so amenable to
quick-and-dirty coding. As a final thought it is likely that many
hardware engineers will one day be bi-lingual in both VHDL and
Verilog.
Can I use VHDL for the analog part of a design?
No. You can't design analog circuitry in VHDL,
however you can model analogue circuitry in VHDL
(said this digital designer!). In theory, VHDL can be used to
model the behaviour of any system or component. However, VHDL
does not offer the same level of modeling accuracy as say Spice,
without an awful lot of work (start writing those differential
equation solvers, now). For examples of using VHDL to model
analogue circuitry, check out:
For information on the Analog Working Group (1076.1) that is engaged in providing analogue design capabilities within VHDL, please try the Analogue Home Page.
How must I write VHDL to make it synthesisable?
Writing VHDL for synthesis is not particularly difficult, but you
need to be disciplined, not only in your use of VHDL syntax but
also your approach to writing VHDL for synthesis. It is this
latter aspect which many engineers overlook; thorough training is
really the only way to avoid making poor strategy decisions in
writing synthesisable VHDL. Check out our Tip of the Month for March 1996
in order to gain an appreciation of the issues involved.
How many versions of VHDL are there?
There are two. The original release of the VHDL language occured
in 1987 with the adoption of the Language Reference Manual as an
IEEE standard. In 1993, the IEEE-1076 standard was modified and
ratified and became known as VHDL'93. At the current time, the
only simulator we know of that claims to offer full VHDL'93
support is Model Technology's V-System simulator.
A VHDL design can be moved to any tool or technology.
Right?
On the face of it, this is true. VHDL was designed to be and is a
technology independent design language. However, there is less of
a compliance issue between different simulators than there is for
synthesis tools. Generally speaking, moving VHDL code from one
simulator to another involves one or two minor changes to the
VHDL. Two different synthesis tools may support two quite
different VHDL subsets. This is particularly an issue for us at
Doulos in developing our training courses, because we like to
present a reasonably generic approach to writing VHDL for
synthesis. This means that the VHDL we teach you is guaranteed to
be more transportable between synthesis tools than it otherwise
would be. Our pain is your gain! In addition because we are so
aware of the differences between synthesis tools, this means that
we emphasise the best way of writing VHDL to get the best from
your synthesis tool.
Are there any tools to generate VHDL test benches
automatically?
A quick scan of the Internet reveals that there are no automatic
testbench generation tools. The VH Structural Code Generator
which is shipped with the Doulos VHDL PaceMaker Project Edition
will give you a testbench template, but you'll still have to fill
in the stimulus and monitoring sections. You should bear in mind
that the creation of functional tests for your VHDL designs is
one of the major tasks involved in designing with VHDL.
Can you give me a measure of the productivity
improvements I should expect from VHDL?
Well, do you believe the hype! Yes, ultimately there are
considerable productivity gains to be had from using high-level
design techniques in conjunction with synthesis technology,
providing that your designs are: complex amenable to synthesis
not dependent upon the benefits of a particular technology
Obviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let's face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into HLD. Of course, once you are benefiting from HLD productivity gains, the specification phase becomes more significant. OK, that's HLD: VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process. However, you won't get those benefits immediately. Your first VHDL-based project will probably take slightly longer than if you had used your previous design process. Where you really win out is second time around. In order to reduce the time spent on your first project and to ensure that subsequent projects benefit from good VHDL design practices, you need to ensure that your engineers are well trained (well, we would say that wouldn't we!)
Are there translators from 'C' to VHDL?
Once again, a quick surf of the Internet reveals that there are
no C to VHDL translators. There are a few Verilog to VHDL
translators, however, a visit to FAQ
comp.lang.vhdl part 3 will be of interest if you need a
translator. For including C routines into your VHDL code, VHDL'93
defines the foreign attribute for subprograms. This allows you to
call object code from within your VHDL simulation. Note that the
source code language for the routine is un-defined - it could be
Pascal or Lisp, for example; the format of the object code though
must be supported by the simulator.
I can see how to write abstract behavioural
descriptions in VHDL, but how do you describe and simulate the
actual hardware?
This is probably the biggest hurdle that many hardware engineers
face when moving to VHDL. After all, sometimes we need to be able
to describe actual implementation as well as abstract
functionality. The way to describe "physical" hardware
in VHDL is to write VHDL models of those components. This is
supported in VHDL through the use of instantiation. VHDL does not
allow you to physically simulate your hardware. You can only
simulate a model of that component in a VHDL simulation.
Historically, gate-level simulation using VHDL has been
notoriously slow. This led to the creation of the 1076.4 working
group to provide a mechanism to allow fast gate-level simulation
using VHDL. Their effort became known as the VITAL standard.
VITAL is not a VHDL issue for you, but an EDA vendor/ASIC
supplier issue. A simulator is VITAL compliant if it implements
the VITAL package in its kernel (this is faster than simulating
the VITAL primitives in the VITAL package). You don't need to
change your VHDL netlist; your ASIC vendor needs to have a VITAL
compliant library though, in order for you to take advantage of
the simulation speed up. Thus the ASIC vendor's library elements
need to be implemented entirely in VITAL primitives.
I've heard that VHDL is very inefficient for FPGAs. Is
that true?
How can VHDL be inefficient for FPGA design? It's a hardware
description language. Of course, the problem is with synthesising
VHDL to FPGA target technology. Generally, synthesis tools are
developed for ASIC target technology, particularly gate arrays,
whose architecture is fine-grained, that is a sea of simple gates
(2, 3, 4-input AND, OR gates, single flip-flops, etc) This is
obviously a mismatch to the architecture of most FPGAs, with
their CLB (complex logic block) coarse-grained structure. This
problem has been tackled in two ways. Crosspoint FPGAs mimic the
fine-grained structure of ASICs in order to allow you to use
conventional ASIC synthesis tools. The more common approach has
been for EDA vendors to develop FPGA-specific algorithms as part
of an existing synthesis tool (for example, Synopsys' FPGA
Compiler) or to develop FPGA-specific synthesis tools (for
example Neocad's tools, now owned by Xilinx).
Are there any VHDL source code libraries available to
save me having to re-invent common code fragments and functions?
There are a few libraries available for most levels of VHDL
design. The IEEE library contains very low-level
type-and-function packages. The std_logic_1164 package has become
an industry standard. Hardly anyone writes a re-usable VHDL
component without using this package for the STD_LOGIC and
STD_LOGIC_VECTOR type definitions. For libraries of components,
Doulos offer a Model Library as part of the VHDL PaceMaker
Project Edition. The VHDL Technology Group offer a range of
functions and models for VHDL programmers.
Are freeware / shareware VHDL tools available?
Generally, the answer is no. Some EDA vendors offer limited use
demo versions of their tools. For example, Accolade provide a
demo version of their EDA package. The Alliance tool suite
including simulation and synthesis tools is available via
anonymous FTP from cao-vlsi.ibp.fr/pub/alliance. Details on more
tools can be found at FAQ
comp.lang.vhdl part 3.
Are there any inexpensive VHDL tools available?
Yes, there are one or two. Cypress Semiconductor offer a low-cost
simulation and synthesis toolset for their PLDs. For
general-purpose use, Green Mountain offer a low-cost compiler,
see FAQ
comp.lang.vhdl part 3.
What is Synthesis?
Synthesis is the stage in the design flow which is concerned with
translating your VHDL code into gates - and that's putting it very
simply! First of all, the VHDL must be written in a
particular way for the synthesis tool that you are using. Of
course, a synthesis tool doesn't actually produce gates - it will
output a netlist of the design that you have synthesised that
represents the chip which can be fabricated through an ASIC or
FPGA vendor.
Are there many books on VHDL?
Yes, there are quite a few these days. Check out the booklist
kept at VHDL
UK Home Page - there are even some reviews here, too.
How about on-line information resources?
You’re already here! Try the VHDL section of
our High Level Design Library for examples of VHDL models and
assorted tips and tricks. On our “Where to go next...”
page you’ll find links to other EDA-related Web sites. In
addition, check out the comp.lang.vhdl
newsgroup.
Where to go next...
Doulos Training Courses
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This page was last updated 26th March 1996.
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