Medium Scale Integrated (MSI) Circuit Models

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RASSP VITAL Modeling Effort at Georgia Institute of Technology: 4x4 Ripple Carry Adder, 4 bit Arithmetic Shifter, 4 bit Barrel Shifter,; and 4x4 Carry Save Multiplier; Point of Contact: Dr. Vijay Madisetti; VITAL Compliant Models with WAVES Testbenches; General Taxonomy Level : VITAL Compliant; Created by : Georgia Institute of Technology/ Digital Signal Processing Laboratory
Parity Generators -- a tar file: Description : 6 through 14 input parity generators; General Taxonomy Level : Behavioral and Structural; Created by :
SN54S151: Description : SN54S151 8-input Data Selector/Multiplexer; General Taxonomy Level : Dataflow; Created by : Steve Frezza
4-bit serial Adder -- a compressed tar file: Description : 4-bit serial Adder; General Taxonomy Level : Structural; Created by : Jiyong Ahn
Armstrong Counter: Description : The Armstrong counter counts up or down and the; counting stops when limits are reached; General Taxonomy Level : Behavioral; Created by : Champaka Ramachandran; University Of California, Irvine
8-bit Barrel Shifter -- VHDL file: Description : 8-bit Barrel Shifter implemented as a tree shifter; with three stages; General Taxonomy Level : Dataflow; Created by : Alan R. Martello, University of Pittsburgh
4-bit Register model: Description : 4-bit register models; General Taxonomy Level : Behavioral and Structural models; Created by :
Various Synthesizable MSI Models: Description : Various Synthesizable MSI models at multiple; levels of abstraction; General Taxonomy Level : Behavioral, RTL, and Gate level; Created by :
Generic 74X244 type tri-state buffer -- a compressed tar file: Description : Generic 74X244 type tri-state expandable buffer; General Taxonomy Level : RTL; Created by : Tom Rust and Don Day (RGB Spectrum); Email: tom@rgb.com, don@rgb.com
Multilevel Pipeline Register with Output Enable -- a compressed tar file: Description : 29fct520 Multilevel Pipeline Register with Output Enable; General Taxonomy Level : RTL; Created by : Tom Rust and Don Day (RGB Spectrum); Email: tom@rgb.com, don@rgb.com
Register Model with Output Enable -- a compressed tar file: Description : Generic register model of length N with output enable; General Taxonomy Level : RTL; Created by : Tom Rust and Don Day (RGB Spectrum); Email: tom@rgb.com, don@rgb.com
Generic Transceiver -- a compressed tar file: Description : Generic transceiver model; General Taxonomy Level : RTL; Created by : Tom Rust and Don Day (RGB Spectrum); Email: tom@rgb.com, don@rgb.com
Latched Transceiver -- a compressed tar file: Description : Latched transceiver model; General Taxonomy Level : Behavioral; Created by : Tom Rust and Don Day (RGB Spectrum); Email: tom@rgb.com, don@rgb.com
Register Unit -- VHDL file (Here): Description : Synthesizable Register Unit from Mentor Graphics; General Taxonomy Level : RTL; Created by : T.Ohtsuka; Email: tootsuka@ss.titech.ac.jp

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