This directory contains a number of reports which have been developed
as part of the EDIF Technical Centre's work on various ECIP
work packages.

Currently three reports are available which have been completed as part
of ECIP work package 1 (WP1).  These relate to EXPRESS and it's
ability to model time related behaviour.  The reports are stored as
compressed postscript in the following files:

These files are being publically released for review and comment.  If
you are worried about the copyright notice on the first page please
contact us (edif-support@cs.man.ac.uk) and we will try and send you
something suitable in writing allowing rights to use, review and comment
on the reports.

time-models.ps.Z
Report ECIP2/UM/009-2  12-11-92

This report presents several variants of a time model relying
on time space structure rather than on numerical values used to
measure time. The model observes common sense time properties and can
be used in modelling time based behaviour of various artifacts.
Discrete versus continuous time modelling is also discussed and it is
shown that the model can cope with both. The ability to provide a
fundamental model of time is essential to the use of information
modelling of domains such as VHDL.



VHDL-model.ps.Z
Report ECIP2/UM/015-1 01-05-93 ``An Information Model of VHDL''

This report addresses the information modelling of both structural and
behavioural aspects of VHDL.  It is an attempt to produce an almost
complete core model of VHDL form the structural, elaboration,
behavioural and execution points of view.  However, the VHDL
computational aspects such as procedures, variables, expressions which
would clutter the model with unnecessary information, are avoided.''
This report supersedes the earlier report, ECIP2/UM/008-1



old-VHDL-model.ps.Z
Preliminary Report ECIP2/UM/008-1  22-10-92 ``Towards A VHDL Model''

This report addresses time-based behaviour modelling in hardware
design, particularly for VHDL. Its main purpose is to propose a way
time-dependent behaviour, in particular VHDL behaviour, can be
modelled by using simple conceptual relationships. In addition, it
presents an outline model of VHDL behaviour in EXPRESS.