-- Copyright (c) 1989 Vantage Analysis Systems, Inc -- This source file may be used and distributed -- without restriction provided that the copyright -- is not removed and that the code is not used -- or distributed for profit. -------------------------------------------------------------------------- -- copyright 1988 -- Vantage Analysis Systems, Inc. -- all rights reserved -- -- File name : std_logic.vhdl -- Title : STD_LOGIC package VHDL source -- Subsystem : analyzer -- Module : VHDL source -- -- Purpose : source for STD_LOGIC package -- -- Author(s) : dlp,kes,drc,ast -- -- Revision : 1/14/89 -- 1/20/89 -- -- Remarks : Defines the types for the standard logic value -- system and also some functions and arrays to access parts -- of a standard logic value. Also provided are standard logic -- functions on these logic values. -- -------------------------------------------------------------------------- --################################################################################## --################################################################################## --################## ################## --################## PACKAGE INTERFACE ################## --################## ################## --################################################################################## --################################################################################## PACKAGE std_logic IS --$ !VANTAGE_METACOMMENTS_ON --$ !VANTAGE_DNA_ON -- *************************************************************************** -- -- PUBLIC TYPE DECLARATIONS. -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- t_logic: std-value type used in simulation. -- ------------------------------------------------------------------------------ TYPE t_logic IS ( U, D, Z0, Z1, ZDX, DZX, ZX, W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX, R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX ); ------------------------------------------------------------------------------ -- -- t_logic_vector: An array of std-state values. -- ------------------------------------------------------------------------------ TYPE t_logic_vector IS ARRAY(NATURAL RANGE <>) OF t_logic; ------------------------------------------------------------------------------ -- -- f_logic_bus: Resolution function to be used on all signals of type t_wlogic. -- ------------------------------------------------------------------------------ FUNCTION f_logic_bus( s : t_logic_vector ) RETURN t_logic; ------------------------------------------------------------------------------ -- -- t_wlogic: std-state type declaration to be used with all signal declarations. -- ------------------------------------------------------------------------------ SUBTYPE t_wlogic IS f_logic_bus t_logic; ------------------------------------------------------------------------------ -- -- t_wlogic_vector: An array of std-state values. To be used in declaring -- signal arrays of std-state types. -- ------------------------------------------------------------------------------ TYPE t_wlogic_vector IS ARRAY(NATURAL RANGE <>) OF t_wlogic; ------------------------------------------------------------------------------ -- -- t_state: The three basic state values. -- ------------------------------------------------------------------------------ TYPE t_state IS ( '0', '1', 'X' ); ------------------------------------------------------------------------------ -- -- t_strength: The different strengths, in ascending order. -- ------------------------------------------------------------------------------ TYPE t_strength IS ( 'U', 'Z', 'W', 'R', 'F' ); ------------------------------------------------------------------------------ -- -- t_technology: The different technologies supported by this package. -- ------------------------------------------------------------------------------ TYPE t_technology IS ( ecl, cmos, nmos, ttl, ttloc ); ------------------------------------------------------------------------------ -- -- Internal Types: Types for look-up tables: -- f_state_T : Takes t_logic value, returns the t_state. -- f_strength_T : Takes t_logic value, returns the t_strength. -- f_logic_T : Takes t_logic value, converts to different t_logic. -- -- F_1_X_1 : Takes t_state, converts to a different t_state. -- (ie, f_convz, f_not) -- F_2_X_1 : Takes 2 t_state values, converts to new t_state. -- (ie, f_and, f_or, f_nand, f_nor, f_xor) -- -- f_str : Used in f_log_con_t. -- f_log_con_t : Takes t_state and t_strength, returns t_logic. -- -- f_tech_con : Used in f_tech_T. -- f_tech_T : Takes t_state and t_technology, returns t_logic. -- f_specific_T : Takes t_state, returns t_logic based on technology. -- -- f_boolean_T : Takes t_logic, returns boolean. -- ------------------------------------------------------------------------------ TYPE f_state_T IS ARRAY (t_logic'low to t_logic'high) OF t_state; TYPE f_strength_T IS ARRAY (t_logic'low to t_logic'high) OF t_strength; TYPE f_logic_T IS ARRAY (t_logic'low to t_logic'high) OF t_logic; TYPE F_1_X_1 IS ARRAY (t_state'low to t_state'high) OF t_state; TYPE F_2_X_1 IS ARRAY (t_state'low to t_state'high) OF F_1_X_1; TYPE f_str IS ARRAY (t_strength'low to t_strength'high) OF t_logic; TYPE f_log_con_T IS ARRAY (t_state'low to t_state'high) OF f_str; TYPE f_logs_con_t IS ARRAY (t_strength'LOW TO t_strength'HIGH) OF f_str; TYPE f_tech_con IS ARRAY (t_technology'low to t_technology'high) OF t_logic; TYPE f_tech_T IS ARRAY (t_state'low to t_state'high) OF f_tech_con; type f_specific_t is array( t_state'low to t_state'high ) of t_logic; type f_boolean_t is array( t_logic'low to t_logic'high ) of boolean; -- *************************************************************************** -- -- PUBLIC OVERLOADED COMPARISON OPERATORS DECLARATIONS. -- -- *************************************************************************** FUNCTION "=" ( l : t_logic; r : t_state ) RETURN boolean; FUNCTION "=" ( l : t_state; r : t_logic ) RETURN boolean; FUNCTION "/=" ( l : t_logic; r : t_state ) RETURN boolean; FUNCTION "/=" ( l : t_state; r : t_logic ) RETURN boolean; FUNCTION ">" ( l : t_logic; r : t_state ) RETURN boolean; FUNCTION ">" ( l : t_state; r : t_logic ) RETURN boolean; FUNCTION ">=" ( l : t_logic; r : t_state ) RETURN boolean; FUNCTION ">=" ( l : t_state; r : t_logic ) RETURN boolean; FUNCTION "<" ( l : t_logic; r : t_state ) RETURN boolean; FUNCTION "<" ( l : t_state; r : t_logic ) RETURN boolean; FUNCTION "<=" ( l : t_logic; r : t_state ) RETURN boolean; FUNCTION "<=" ( l : t_state; r : t_logic ) RETURN boolean; -- *************************************************************************** -- -- PUBLIC TABLE (CONSTANT) DECLARATIONS. -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- table name: f_state -- parameters: -- in logic -- t_logic -- logic value -- -- returns: t_state -- state value from logic value -- -- purpose: Take a logic value, and return the state -- -- example: -- IF (f_state( input_signal ) = '1') THEN -- -- Some statements -- ELSIF (f_state( input_signal ) = '0') THEN -- -- Some statements -- ELSE -- -- Some statements -- END IF; -- ------------------------------------------------------------------------------ -- Given value return the associated state CONSTANT f_state : f_state_t := ( 'X', -- U 'X', -- D '0', -- Z0 '1', -- Z1 'X', -- ZDX 'X', -- DZX 'X', -- ZX '0', -- W0 '1', -- W1 '0', -- WZ0 '1', -- WZ1 'X', -- WDX 'X', -- DWX 'X', -- WZX 'X', -- ZWX 'X', -- WX '0', -- R0 '1', -- R1 '0', -- RW0 '1', -- RW1 '0', -- RZ0 '1', -- RZ1 'X', -- RDX 'X', -- DRX 'X', -- RZX 'X', -- ZRX 'X', -- RWX 'X', -- WRX 'X', -- RX '0', -- F0 '1', -- F1 '0', -- FR0 '1', -- FR1 '0', -- FW0 '1', -- FW1 '0', -- FZ0 '1', -- FZ1 'X', -- FDX 'X', -- DFX 'X', -- FZX 'X', -- ZFX 'X', -- FWX 'X', -- WFX 'X', -- FRX 'X', -- RFX 'X' -- FX ); ------------------------------------------------------------------------------ -- -- table name: f_strength -- parameters: -- in logic -- t_logic -- logic value -- -- returns: t_strength -- strength value from logic value -- -- purpose: Take a logic value, and return the strength portion of that value. -- -- notes: This function will return the strongest strength always. For -- instance when given QR00 it will return R as the strength. -- -- example: -- IF (f_strength( input_signal ) = 'U') THEN -- -- Some statements -- ELSIF (f_strength( input_signal ) = 'F') THEN -- -- Some statements -- ELSE -- -- Some statements -- END IF; -- ------------------------------------------------------------------------------ -- Given logic value return the strength CONSTANT f_strength : f_strength_t := ( 'F', -- U 'U', -- D 'Z', -- Z0 'Z', -- Z1 'Z', -- ZDX 'Z', -- DZX 'Z', -- ZX 'W', -- W0 'W', -- W1 'W', -- WZ0 'W', -- WZ1 'W', -- WDX 'W', -- DWX 'W', -- WZX 'W', -- ZWX 'W', -- WX 'R', -- R0 'R', -- R1 'R', -- RW0 'R', -- RW1 'R', -- RZ0 'R', -- RZ1 'R', -- RDX 'R', -- DRX 'R', -- RZX 'R', -- ZRX 'R', -- RWX 'R', -- WRX 'R', -- RX 'F', -- F0 'F', -- F1 'F', -- FR0 'F', -- FR1 'F', -- FW0 'F', -- FW1 'F', -- FZ0 'F', -- FZ1 'F', -- FDX 'F', -- DFX 'F', -- FZX 'F', -- ZFX 'F', -- FWX 'F', -- WFX 'F', -- FRX 'F', -- RFX 'F' -- FX ); -- Given logic value return the strength CONSTANT f_strengthL : f_strength_t := ( 'F', -- U 'U', -- D 'Z', -- Z0 'Z', -- Z1 'Z', -- ZDX 'U', -- DZX 'Z', -- ZX 'W', -- W0 'W', -- W1 'Z', -- WZ0 'Z', -- WZ1 'W', -- WDX 'U', -- DWX 'W', -- WZX 'Z', -- ZWX 'W', -- WX 'R', -- R0 'R', -- R1 'W', -- RW0 'W', -- RW1 'Z', -- RZ0 'Z', -- RZ1 'R', -- RDX 'U', -- DRX 'R', -- RZX 'Z', -- ZRX 'R', -- RWX 'W', -- WRX 'R', -- RX 'F', -- F0 'F', -- F1 'R', -- FR0 'R', -- FR1 'W', -- FW0 'W', -- FW1 'Z', -- FZ0 'Z', -- FZ1 'F', -- FDX 'U', -- DFX 'F', -- FZX 'Z', -- ZFX 'F', -- FWX 'W', -- WFX 'F', -- FRX 'R', -- RFX 'F' -- FX ); -- Given logic value return the strength CONSTANT f_strengthH : f_strength_t := ( 'F', -- U 'U', -- D 'Z', -- Z0 'Z', -- Z1 'U', -- ZDX 'Z', -- DZX 'Z', -- ZX 'W', -- W0 'W', -- W1 'W', -- WZ0 'W', -- WZ1 'U', -- WDX 'W', -- DWX 'Z', -- WZX 'W', -- ZWX 'W', -- WX 'R', -- R0 'R', -- R1 'R', -- RW0 'R', -- RW1 'R', -- RZ0 'R', -- RZ1 'U', -- RDX 'R', -- DRX 'Z', -- RZX 'R', -- ZRX 'W', -- RWX 'R', -- WRX 'R', -- RX 'F', -- F0 'F', -- F1 'F', -- FR0 'F', -- FR1 'F', -- FW0 'F', -- FW1 'F', -- FZ0 'F', -- FZ1 'U', -- FDX 'F', -- DFX 'Z', -- FZX 'F', -- ZFX 'W', -- FWX 'F', -- WFX 'R', -- FRX 'F', -- RFX 'F' -- FX ); ------------------------------------------------------------------------------ -- -- table name: f_logic -- parameters: -- in state -- t_state -- state value -- in strength -- t_strength -- strength value -- -- returns: t_logic -- logic value created from inputs -- -- purpose: Takes a state and strength and returns the logic value -- associated with the pair. -- example: -- output_signal <= f_logic( '1' )( 'F' ) AFTER delay; -- F1 -- ------------------------------------------------------------------------------ -- Given state/strength, return logic value CONSTANT f_logic : f_log_con_t := ( ( D , -- '0', 'U' Z0, -- '0', 'Z' W0, -- '0', 'W' R0, -- '0', 'R' F0 ), -- '0', 'F' ( D , -- '1', 'U' Z1, -- '1', 'Z' W1, -- '1', 'W' R1, -- '1', 'R' F1 ), -- '1', 'F' ( D , -- 'X', 'U' ZX, -- 'X', 'Z' WX, -- 'X', 'W' RX, -- 'X', 'R' FX ) -- 'X', 'F' ); -- Given strength/strength, return logic value CONSTANT f_logic0 : f_logs_con_t := ( ( D, -- 'U', 'U' ZDX, -- 'U', 'Z' WDX, -- 'U', 'W' RDX, -- 'U', 'R' FDX ), -- 'U', 'F' ( ZDX, -- 'Z', 'U' Z0, -- 'Z', 'Z' WZ0, -- 'Z', 'W' RZ0, -- 'Z', 'R' FZ0 ), -- 'Z', 'F' ( WDX, -- 'W', 'U' WZ0, -- 'W', 'Z' W0, -- 'W', 'W' RW0, -- 'W', 'R' FW0 ), -- 'W', 'F' ( RDX, -- 'R', 'U' RZ0, -- 'R', 'Z' RW0, -- 'R', 'W' R0, -- 'R', 'R' FR0 ), -- 'R', 'F' ( FDX, -- 'F', 'U' FZ0, -- 'F', 'Z' FW0, -- 'F', 'W' FR0, -- 'F', 'R' F0 ) -- 'F', 'F' ); -- Given strength/strength, return logic value CONSTANT f_logic1 : f_logs_con_t := ( ( D, -- 'U', 'U' DZX, -- 'U', 'Z' DWX, -- 'U', 'W' DRX, -- 'U', 'R' DFX ), -- 'U', 'F' ( DZX, -- 'Z', 'U' Z1, -- 'Z', 'Z' WZ1, -- 'Z', 'W' RZ1, -- 'Z', 'R' FZ1 ), -- 'Z', 'F' ( DWX, -- 'W', 'U' WZ1, -- 'W', 'Z' W1, -- 'W', 'W' RW1, -- 'W', 'R' FW1 ), -- 'W', 'F' ( DRX, -- 'R', 'U' RZ1, -- 'R', 'Z' RW1, -- 'R', 'W' R1, -- 'R', 'R' FR1 ), -- 'R', 'F' ( DFX, -- 'F', 'U' FZ1, -- 'F', 'Z' FW1, -- 'F', 'W' FR1, -- 'F', 'R' F1 ) -- 'F', 'F' ); -- Given strength/strength, return logic value CONSTANT f_logicX : f_logs_con_t := ( ( D, -- 'U', 'U' DZX, -- 'U', 'Z' DWX, -- 'U', 'W' DRX, -- 'U', 'R' DFX ), -- 'U', 'F' ( ZDX, -- 'Z', 'U' ZX, -- 'Z', 'Z' ZWX, -- 'Z', 'W' ZRX, -- 'Z', 'R' ZFX ), -- 'Z', 'F' ( WDX, -- 'W', 'U' WZX, -- 'W', 'Z' WX, -- 'W', 'W' WRX, -- 'W', 'R' WFX ), -- 'W', 'F' ( RDX, -- 'R', 'U' RZX, -- 'R', 'Z' RWX, -- 'R', 'W' RX, -- 'R', 'R' RFX ), -- 'R', 'F' ( FDX, -- 'F', 'U' FZX, -- 'F', 'Z' FWX, -- 'F', 'W' FRX, -- 'F', 'R' FX ) -- 'F', 'F' ); -- *************************************************************************** -- -- TECHNOLOGY LOOKUP TABLES -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- table name: f_ecl, f_cmos, f_nmos, f_ttl, f_ttloc -- parameters: -- in state -- t_state -- state value -- -- returns: t_logic -- logic value created from input and technology. -- -- purpose: Take a state value and the implicit techology of a signal and return -- the logic value associated with an output of that technology. -- -- example: -- new_state := f_and( inp1 )( inp2 ); -- output_signal <= f_ttl( new_state ) AFTER delay; -- ------------------------------------------------------------------------------ -- Technology lookup tables CONSTANT f_ecl : f_specific_t := ( R0, -- '0' F1, -- '1' RFX -- 'X' ); CONSTANT f_cmos : f_specific_t := ( F0, -- '0' F1, -- '1' FX -- 'X' ); CONSTANT f_nmos : f_specific_t := ( F0, -- '0' R1, -- '1' FRX -- 'X' ); CONSTANT f_ttl : f_specific_t := ( F0, -- '0' F1, -- '1' FX -- 'X' ); CONSTANT f_ttloc : f_specific_t := ( F0, -- '0' ZX, -- '1' FZX -- 'X' ); ------------------------------------------------------------------------------ -- -- table name: f_tech -- parameters: -- in state -- t_state -- state value -- in tech -- t_technology -- technology value -- -- returns: t_logic -- logic value created from inputs -- -- purpose: Takes a state value and the techology of a signal and returns -- the logic value associated with an output of that technology. -- -- example: -- new_state := f_and( inp1 )( inp2 ); -- output_signal <= f_tech( new_state )( ttl ) AFTER delay; -- ------------------------------------------------------------------------------ -- Given state and technology, return appropriate output value CONSTANT f_tech : f_tech_t := ( ( R0, -- '0', ecl F0, -- '0', cmos F0, -- '0', nmos F0, -- '0', ttl F0 ), -- '0', ttloc ( F1, -- '1', ecl F1, -- '1', cmos R1, -- '1', nmos F1, -- '1', ttl ZX ), -- '1', ttloc ( RFX, -- 'X', ecl FX, -- 'X', cmos FRX, -- 'X', nmos FX, -- 'X', ttl FZX ) -- 'X', ttloc ); ------------------------------------------------------------------------------ -- -- table name: f_convz -- parameters: -- in logic -- t_logic -- logic value -- -- returns: t_logic -- logic value created from the input. -- -- purpose: Take a logic value, and convert it to the appropriate value with -- high impedance strength. (Z) -- -- notes: This table is useful in calculating the new state of a tristate -- node that has just had the control signal turned off. -- -- example: -- output_signal <= f_convz( input_signal ) AFTER delay; -- ------------------------------------------------------------------------------ -- Given logic value, return appropriate high-impedance tristate logic value CONSTANT f_convz : f_logic_t := ( ZX, -- U D, -- D Z0, -- Z0 Z1, -- Z1 ZDX, -- ZDX DZX, -- DZX ZX, -- ZX Z0, -- W0 Z1, -- W1 Z0, -- WZ0 Z1, -- WZ1 ZDX, -- WDX DZX, -- DWX ZX, -- WZX ZX, -- ZWX ZX, -- WX Z0, -- R0 Z1, -- R1 Z0, -- RW0 Z1, -- RW1 Z0, -- RZ0 Z1, -- RZ1 ZDX, -- RDX DZX, -- DRX ZX, -- RZX ZX, -- ZRX ZX, -- RWX ZX, -- WRX ZX, -- RX Z0, -- F0 Z1, -- F1 Z0, -- FR0 Z1, -- FR1 Z0, -- FW0 Z1, -- FW1 Z0, -- FZ0 Z1, -- FZ1 ZDX, -- FDX DZX, -- DFX ZX, -- FZX ZX, -- ZFX ZX, -- FWX ZX, -- WFX ZX, -- FRX ZX, -- RFX ZX -- FX ); ------------------------------------------------------------------------------ -- -- function name: f_convu -- parameters: -- in newval -- t_logic -- new state value (ONLY STATE -- information is used) -- in lastval -- t_logic -- old state value -- in tech -- t_technology -- technology of gate -- -- returns: t_logic -- strongest possible state -- -- purpose: This function calculates the state that should be output -- from a tristateable output when the gating signal is of an -- unknown value. This function basically calculates the -- strongest possible state that this gate could put out. -- ------------------------------------------------------------------------------ FUNCTION f_convu ( newval : IN t_logic; lastval : IN t_logic; tech : IN t_technology ) RETURN t_logic; ------------------------------------------------------------------------------ -- -- function name: f_convx -- parameters: -- in newval -- t_logic -- new state value (ONLY STATE -- information is used) -- in lastval -- t_logic -- old state value -- in tech -- t_technology -- technology of gate -- -- returns: t_logic -- strongest possible state -- -- purpose: This function calculates the state that should be output -- from a tristateable output when the gating signal is of an -- unknown value. This function basically calculates the -- strongest possible state that this gate could put out. -- ------------------------------------------------------------------------------ FUNCTION f_convx ( newval : IN t_logic; lastval : IN t_logic; tech : IN t_technology ) RETURN t_logic; ------------------------------------------------------------------------------ -- -- function name: f_uxfr -- parameters: -- in G -- t_logic -- in Src -- t_logic -- in Drn -- t_logic -- -- returns: t_logic -- to drive Drn output -- -- purpose: This function calculates the output value of Drn based on the -- current values of G, Src, and Drn. -- if G is on then -- the output to Drn is Src -- elsif G is off then -- the output to Drn is f_convz(Drn) -- else -- the output to Drn is the interval between Src and f_convz(Drn) -- end if; -- ------------------------------------------------------------------------------ FUNCTION f_uxfr ( G,Src,Drn : IN t_logic ) RETURN t_logic; ------------------------------------------------------------------------------ -- -- function name: f_resistor -- parameters: -- in S -- t_logic -- in SIZE -- natural -- -- returns: t_logic -- to drive D output -- -- purpose: This function calculates the output value of D based on the -- current values of S. The strength of S is decreased by SIZE level. -- ------------------------------------------------------------------------------ FUNCTION f_resistor ( S : IN t_logic; SIZE : IN natural ) RETURN t_logic; ------------------------------------------------------------------------------ -- -- function name: f_ceil -- parameters: -- in S -- t_logic -- in SIZE -- t_strength -- -- returns: t_logic -- to drive D output -- -- purpose: This function calculates the output value of D based on the -- current values of S. The strength of S is decreased by SIZE level. -- ------------------------------------------------------------------------------ FUNCTION f_ceil ( S : IN t_logic; SIZE : IN t_strength ) RETURN t_logic; ------------------------------------------------------------------------------ -- -- function name: f_cap -- parameters: -- in S -- t_logic -- in SIZE -- t_strength -- -- returns: t_logic -- to drive D output -- -- purpose: This function implements the capacitor. -- IF the strength of S is larger or equal to the -- size of the capacitor THEN -- RETURN S; -- ELSE -- RETURN the value charged up in the capacitor. -- END IF; -- -- ------------------------------------------------------------------------------ FUNCTION f_cap ( S : IN t_logic; SIZE : IN t_strength ) RETURN t_logic; -- *************************************************************************** -- -- LOGIC LOOKUP TABLES -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- table name: f_and -- parameters: -- in state1 -- t_state -- state value -- in state2 -- t_state -- state value -- -- returns: t_state -- state value created from inputs -- -- purpose: Computes (state1 and state2) and returns its value. -- -- notes: The overloaded "and" operator can be obtained within the -- accompanying "std_ecl", "std_cmos", "std_nmos", "std_ttl" -- or "std_ttloc" packages. -- -- example: -- ASSERT ( f_and( '1' )( '1' ) = '1' ); -- ------------------------------------------------------------------------------ CONSTANT f_and : f_2_x_1 := ( ( '0', -- '0', '0' '0', -- '0', '1', '0' ), -- '0', 'X' ( '0', -- '1', '0' '1', -- '1', '1' 'X' ), -- '1', 'X' ( '0', -- 'X', '0' 'X', -- 'X', '1' 'X' ) -- 'X', 'X' ); ------------------------------------------------------------------------------ -- -- table name: f_or -- parameters: -- in state1 -- t_state -- state value -- in state2 -- t_state -- state value -- -- returns: t_state -- state value created from inputs -- -- purpose: Computes (state1 or state2) and returns its value. -- -- notes: The overloaded "or" operator can be obtained within the -- accompanying "std_ecl", "std_cmos", "std_nmos", "std_ttl" -- or "std_ttloc" packages. -- -- example: -- ASSERT ( f_or( '1' )( '0' ) = '1' ); -- ------------------------------------------------------------------------------ CONSTANT f_or : f_2_x_1 := ( ( '0', -- '0', '0' '1', -- '0', '1', 'X' ), -- '0', 'X' ( '1', -- '1', '0' '1', -- '1', '1' '1' ), -- '1', 'X' ( 'X', -- 'X', '0' '1', -- 'X', '1' 'X' ) -- 'X', 'X' ); ------------------------------------------------------------------------------ -- -- table name: f_nand -- parameters: -- in state1 -- t_state -- state value -- in state2 -- t_state -- state value -- -- returns: t_state -- state value created from inputs -- -- purpose: Computes (state1 nand state2) and returns its value. -- -- notes: The overloaded "nand" operator can be obtained within the -- accompanying "std_ecl", "std_cmos", "std_nmos", "std_ttl" -- or "std_ttloc" packages. -- -- example: -- ASSERT ( f_nand( '1' )( '1' ) = '0' ); -- ------------------------------------------------------------------------------ CONSTANT f_nand : f_2_x_1 := ( ( '1', -- '0', '0' '1', -- '0', '1', '1' ), -- '0', 'X' ( '1', -- '1', '0' '0', -- '1', '1' 'X' ), -- '1', 'X' ( '1', -- 'X', '0' 'X', -- 'X', '1' 'X' ) -- 'X', 'X' ); ------------------------------------------------------------------------------ -- -- table name: f_nor -- parameters: -- in state1 -- t_state -- state value -- in state2 -- t_state -- state value -- -- returns: t_state -- state value created from inputs -- -- purpose: Computes (state1 nor state2) and returns its value. -- -- notes: The overloaded "nor" operator can be obtained within the -- accompanying "std_ecl", "std_cmos", "std_nmos", "std_ttl" -- or "std_ttloc" packages. -- -- example: -- ASSERT ( f_nor( '1' )( '0' ) = '0' ); -- ------------------------------------------------------------------------------ CONSTANT f_nor : f_2_x_1 := ( ( '1', -- '0', '0' '0', -- '0', '1', 'X' ), -- '0', 'X' ( '0', -- '1', '0' '0', -- '1', '1' '0' ), -- '1', 'X' ( 'X', -- 'X', '0' '0', -- 'X', '1' 'X' ) -- 'X', 'X' ); ------------------------------------------------------------------------------ -- -- table name: f_xor -- parameters: -- in state1 -- t_state -- state value -- in state2 -- t_state -- state value -- -- returns: t_state -- state value created from inputs -- -- purpose: Computes (state1 xor state2) and returns its value. -- -- notes: The overloaded "xor" operator can be obtained within the -- accompanying "std_ecl", "std_cmos", "std_nmos", "std_ttl" -- "std_ttloc" packages. -- -- example: -- ASSERT ( f_xor( '1' )( '1' ) = '0' ); -- ------------------------------------------------------------------------------ CONSTANT f_xor : f_2_x_1 := ( ( '0', -- '0', '0' '1', -- '0', '1', 'X' ), -- '0', 'X' ( '1', -- '1', '0' '0', -- '1', '1' 'X' ), -- '1', 'X' ( 'X', -- 'X', '0' 'X', -- 'X', '1' 'X' ) -- 'X', 'X' ); ------------------------------------------------------------------------------ -- -- table name: f_not -- parameters: -- in state -- t_state -- state value -- -- returns: t_state -- state value created from input -- -- purpose: Computes (not state) and returns its value. -- -- notes: The overloaded "not" operator can be obtained within the -- accompanying "std_ecl", "std_cmos", "std_nmos", "std_ttl" -- or "std_ttloc" packages. -- -- example: -- ASSERT ( f_not( '1' ) = '0' ); -- ------------------------------------------------------------------------------ CONSTANT f_not : f_1_x_1 := ( '1', -- '0' '0', -- '1' 'X' -- 'X' ); -- *************************************************************************** -- -- CLOCK EDGE LOOKUP TABLES -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- table name: f_rising_edge -- parameters: -- in logic -- t_logic -- logic value -- -- returns: boolean -- TRUE if state is '1' ('0'), false otherwise. -- -- purpose: Determine whether the state of the signal value passed indicates -- whether the value is the result of a rising (falling) edge. -- -- example: -- IF (f_rising_edge( clk )) THEN -- -- Check the 'setup' constraints on the inputs. -- END IF; -- ------------------------------------------------------------------------------ -- Given value, return true for rising edge CONSTANT f_rising_edge : f_boolean_t := ( false, -- U false, -- D false, -- Z0 true, -- Z1 false, -- ZDX false, -- DZX false, -- ZX false, -- W0 true, -- W1 false, -- WZ0 true, -- WZ1 false, -- WDX false, -- DWX false, -- WZX false, -- ZWX false, -- WX false, -- R0 true, -- R1 false, -- RW0 true, -- RW1 false, -- RZ0 true, -- RZ1 false, -- RDX false, -- DRX false, -- RZX false, -- ZRX false, -- RWX false, -- WRX false, -- RX false, -- F0 true, -- F1 false, -- FR0 true, -- FR1 false, -- FW0 true, -- FW1 false, -- FZ0 true, -- FZ1 false, -- FDX false, -- DFX false, -- FZX false, -- ZFX false, -- FWX false, -- WFX false, -- FRX false, -- RFX false -- FX ); ------------------------------------------------------------------------------ -- -- table name: f_falling_edge -- parameters: -- in logic -- t_logic -- logic value -- -- returns: boolean -- TRUE if state is '1' ('0'), false otherwise. -- -- purpose: Determine whether the state of the signal value passed indicates -- whether the value is the result of a falling (falling) edge. -- -- example: -- IF (f_falling_edge( clk )) THEN -- -- Check the 'setup' constraints on the inputs. -- END IF; -- ------------------------------------------------------------------------------ -- Given value, return true for falling edge CONSTANT f_falling_edge : f_boolean_t := ( false, -- U false, -- D true, -- Z0 false, -- Z1 false, -- ZDX false, -- DZX false, -- ZX true, -- W0 false, -- W1 true, -- WZ0 false, -- WZ1 false, -- WDX false, -- DWX false, -- WZX false, -- ZWX false, -- WX true, -- R0 false, -- R1 true, -- RW0 false, -- RW1 true, -- RZ0 false, -- RZ1 false, -- RDX false, -- DRX false, -- RZX false, -- ZRX false, -- RWX false, -- WRX false, -- RX true, -- F0 false, -- F1 true, -- FR0 false, -- FR1 true, -- FW0 false, -- FW1 true, -- FZ0 false, -- FZ1 false, -- FDX false, -- DFX false, -- FZX false, -- ZFX false, -- FWX false, -- WFX false, -- FRX false, -- RFX false -- FX ); -- *************************************************************************** -- -- TIMING UTILITY FUNCTIONS -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- function name: f_delay -- parameters: -- in newlv -- t_logic -- new logic value -- in delay01 -- time -- 0->1 delay value -- in delay10 -- time -- 1->0 delay value -- -- returns: The appropriate delay to be used, given the new value -- and the 0-1 and 1-0 delays. -- -- purpose: Compute the appropriate delay to be used for a transition -- on an output port. -- ------------------------------------------------------------------------------ FUNCTION f_delay( newlv : IN t_logic; delay01 : IN time; delay10 : IN time) RETURN time; ------------------------------------------------------------------------------ -- -- function name: f_zdelay -- parameters: -- in oldlv -- t_logic -- old logic value -- in newlv -- t_logic -- new logic value -- in delay01 -- time -- 0->1 delay value -- in delay10 -- time -- 1->0 delay value -- in delayz0 -- time -- z->0 delay value -- in delayz1 -- time -- z->1 delay value -- in delay0z -- time -- 0->z delay value -- in delay1z -- time -- 1->z delay value -- -- returns: time -- The appropriate delay to be used. -- -- purpose: Compute the delay to schedule for a tristate output based on -- the transistion of the output. If the output is going to a 1 -- from 0 then use the 0->1 delay, which is delay01. If the output -- is going from a 1->z value the use the delay1z value. etc. -- ------------------------------------------------------------------------------ FUNCTION f_zdelay( oldlv : IN t_logic; newlv : IN t_logic; delay01 : IN time; delay10 : IN time; delayz0 : IN time; delayz1 : IN time; delay0z : IN time; delay1z : IN time) RETURN time; ------------------------------------------------------------------------------ -- -- function name: f_setup_check -- parameters: -- signal in signal_to_check -- t_logic -- Signal to be checked for -- setup violations. -- in Setup_Constraint -- time -- 'Signal_to_Check' must have -- been stable for at least -- this amount of time. -- -- returns: boolean -- false if setup time on input is too small. -- -- purpose: Checks to see that the setup time is not violated between the -- data and clock inputs. -- -- example: -- -- -- 'Setup' checking on a positive-edge triggered clock. -- setup_check: PROCESS( clk ) -- BEGIN -- -- -- Only perform the assertion after the rising edge. -- IF (f_rising_edge( clk )) THEN -- -- -- Verify that the setup constraint has not been violated. -- ASSERT( f_setup_check( signal_to_check, setup_constraint ) ) -- REPORT "Setup check violation on 'signal_to_check'." -- SEVERITY error; -- END IF; -- END PROCESS setup_check; -- ------------------------------------------------------------------------------ FUNCTION f_setup_check( SIGNAL signal_to_check : IN t_logic; setup_constraint : IN time ) RETURN boolean; ------------------------------------------------------------------------------ -- -- function name: f_pulse_check -- parameters: -- signal in signal_to_check -- t_logic -- Signal to be checked for -- a minimum pulse width. -- in Minimum_Width -- time -- Minimum width of the -- pulse for this signal. -- -- returns: boolean -- False if pulse width on input is too small. -- -- purpose: Checks to make sure that a pulse on the 'signal_to_check' is not -- narrower than the time specified in width. -- -- example: -- -- -- Positive pulse checking. -- pulse_check: PROCESS( clk ) -- BEGIN -- -- -- Only perform the assertion after the clock falls. -- IF (f_falling_edge( clk )) THEN -- -- -- Verify that the pulse width constraint has not been violated. -- ASSERT( f_pulse_check( clk, minimum_width ) ) -- REPORT "Pulse check violation on 'clk'." -- SEVERITY error; -- END IF; -- END PROCESS pulse_check; -- ------------------------------------------------------------------------------ FUNCTION f_pulse_check( SIGNAL signal_to_check : IN t_logic; minimum_width : IN time ) RETURN boolean; ------------------------------------------------------------------------------ -- -- function name: f_hold_check -- parameters: -- signal in signal_to_check -- t_logic -- Signal to be checked for -- Hold violations. -- in hold_time -- time -- Hold time constraint. -- -- returns: boolean -- False if hold time on input is too small. -- -- purpose: Checks to see that the hold time of the input signal is long -- enough compared to the clock input. -- -- -- notes: To use this function properly, you must wait for 'hold_time' -- after the clock pulse and then call this function. -- -- example: -- -- -- Positive-edge triggered hold time checking process. -- hold_check: PROCESS( clk'DELAYED( holdtime ) ) -- BEGIN -- -- -- Only perform the assertion after the rising edge. -- IF (f_rising_edge( clk'DELAYED( holdtime ) )) THEN -- -- -- Verify that the hold constraint has not been violated. -- ASSERT( f_hold_check( signal_to_check, holdtime ) ) -- REPORT "Hold check violation on 'signal_to_check'." -- SEVERITY error; -- END IF; -- END PROCESS hold_check; -- ------------------------------------------------------------------------------ FUNCTION f_hold_check( SIGNAL signal_to_check : IN t_logic; hold_time : IN time ) RETURN boolean; -- *************************************************************************** -- -- BUS RESOLUTION TABLE LOOKUP -- -- *************************************************************************** -- ------------------------------------------------------------------------------ -- -- table name: f_busres -- parameters: -- in oldst -- t_logic -- old value -- in newst -- t_logic -- new value -- -- returns: t_logic-- Combined value value created from inputs. -- -- purpose: Given two values return the appropriate value -- note: In essense, these tables perform interval analysis returning -- the largest interval spanning two given values ------------------------------------------------------------------------------ -- Type definitions for table TYPE t_bus IS ARRAY(t_logic'LOW TO t_logic'HIGH) OF t_logic; TYPE t_bus_tab IS ARRAY(t_logic'LOW TO t_logic'HIGH) OF t_bus; CONSTANT f_busres : t_bus_tab := ( ( U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U, U ), -- U ( U, D, Z0, Z1, ZDX, DZX, ZX, W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX, R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX ), -- D ( U, Z0, Z0, ZX, Z0, ZX, ZX, W0, W1, WZ0, ZWX, WZ0, ZWX, WZX, ZWX, WX, R0, R1, RW0, RW1, RZ0, ZRX, RZ0, ZRX, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZ0, ZFX, FZ0, ZFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX ), -- Z0 ( U, Z1, ZX, Z1, ZX, Z1, ZX, W0, W1, WZX, WZ1, WZX, WZ1, WZX, ZWX, WX, R0, R1, RW0, RW1, RZX, RZ1, RZX, RZ1, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZX, FZ1, FZX, FZ1, FZX, ZFX, FWX, WFX, FRX, RFX, FX ), -- Z1 ( U, ZDX, Z0, ZX, ZDX, ZX, ZX, W0, W1, WZ0, ZWX, WDX, ZWX, WZX, ZWX, WX, R0, R1, RW0, RW1, RZ0, ZRX, RDX, ZRX, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZ0, ZFX, FDX, ZFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX ), --ZDX ( U, DZX, ZX, Z1, ZX, DZX, ZX, W0, W1, WZX, WZ1, WZX, DWX, WZX, ZWX, WX, R0, R1, RW0, RW1, RZX, RZ1, RZX, DRX, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZX, FZ1, FZX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX ), --DZX ( U, ZX, ZX, ZX, ZX, ZX, ZX, W0, W1, WZX, ZWX, WZX, ZWX, WZX, ZWX, WX, R0, R1, RW0, RW1, RZX, ZRX, RZX, ZRX, RZX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, FW1, FZX, ZFX, FZX, ZFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX ), -- ZX ( U, W0, W0, W0, W0, W0, W0, W0, WX, W0, WX, W0, WX, W0, WX, WX, R0, R1, RW0, WRX, RW0, WRX, RW0, WRX, RW0, WRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, WFX, FW0, WFX, FW0, WFX, FW0, WFX, FWX, WFX, FRX, RFX, FX ), -- W0 ( U, W1, W1, W1, W1, W1, W1, WX, W1, WX, W1, WX, W1, WX, W1, WX, R0, R1, RWX, RW1, RWX, RW1, RWX, RW1, RWX, RW1, RWX, WRX, RX, F0, F1, FR0, FR1, FWX, FW1, FWX, FW1, FWX, FW1, FWX, FW1, FWX, WFX, FRX, RFX, FX ), -- W1 ( U, WZ0, WZ0, WZX, WZ0, WZX, WZX, W0, WX, WZ0, WX, WZ0, WX, WZX, WX, WX, R0, R1, RW0, WRX, RZ0, WRX, RZ0, WRX, RZX, WRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, WFX, FZ0, WFX, FZ0, WFX, FZX, WFX, FWX, WFX, FRX, RFX, FX ),--WZ0 ( U, WZ1, ZWX, WZ1, ZWX, WZ1, ZWX, WX, W1, WX, WZ1, WX, WZ1, WX, ZWX, WX, R0, R1, RWX, RW1, RWX, RZ1, RWX, RZ1, RWX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FWX, FW1, FWX, FZ1, FWX, FZ1, FWX, ZFX, FWX, WFX, FRX, RFX, FX ),--WZ1 ( U, WDX, WZ0, WZX, WDX, WZX, WZX, W0, WX, WZ0, WX, WDX, WX, WZX, WX, WX, R0, R1, RW0, WRX, RZ0, WRX, RDX, WRX, RZX, WRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, WFX, FZ0, WFX, FDX, WFX, FZX, WFX, FWX, WFX, FRX, RFX, FX ),--WDX ( U, DWX, ZWX, WZ1, ZWX, DWX, ZWX, WX, W1, WX, WZ1, WX, DWX, WX, ZWX, WX, R0, R1, RWX, RW1, RWX, RZ1, RWX, DRX, RWX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FWX, FW1, FWX, FZ1, FWX, DFX, FWX, ZFX, FWX, WFX, FRX, RFX, FX ),--DWX ( U, WZX, WZX, WZX, WZX, WZX, WZX, W0, WX, WZX, WX, WZX, WX, WZX, WX, WX, R0, R1, RW0, WRX, RZX, WRX, RZX, WRX, RZX, WRX, RWX, WRX, RX, F0, F1, FR0, FR1, FW0, WFX, FZX, WFX, FZX, WFX, FZX, WFX, FWX, WFX, FRX, RFX, FX ),--WZX ( U, ZWX, ZWX, ZWX, ZWX, ZWX, ZWX, WX, W1, WX, ZWX, WX, ZWX, WX, ZWX, WX, R0, R1, RWX, RW1, RWX, ZRX, RWX, ZRX, RWX, ZRX, RWX, WRX, RX, F0, F1, FR0, FR1, FWX, FW1, FWX, ZFX, FWX, ZFX, FWX, ZFX, FWX, WFX, FRX, RFX, FX ),--ZWX ( U, WX, WX, WX, WX, WX, WX, WX, WX, WX, WX, WX, WX, WX, WX, WX, R0, R1, RWX, WRX, RWX, WRX, RWX, WRX, RWX, WRX, RWX, WRX, RX, F0, F1, FR0, FR1, FWX, WFX, FWX, WFX, FWX, WFX, FWX, WFX, FWX, WFX, FRX, RFX, FX ),--WX ( U, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, RX, R0, RX, R0, RX, R0, RX, R0, RX, R0, RX, RX, F0, F1, FR0, RFX, FR0, RFX, FR0, RFX, FR0, RFX, FR0, RFX, FR0, RFX, FRX, RFX, FX ),--R0 ( U, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, RX, R1, RX, R1, RX, R1, RX, R1, RX, R1, RX, R1, RX, F0, F1, FRX, FR1, FRX, FR1, FRX, FR1, FRX, FR1, FRX, FR1, FRX, FR1, FRX, RFX, FX ),--R1 ( U, RW0, RW0, RW0, RW0, RW0, RW0, RW0, RWX, RW0, RWX, RW0, RWX, RW0, RWX, RWX, R0, RX, RW0, RX, RW0, RX, RW0, RX, RW0, RX, RWX, RX, RX, F0, F1, FR0, RFX, FW0, RFX, FW0, RFX, FW0, RFX, FW0, RFX, FWX, RFX, FRX, RFX, FX ),--RW0 ( U, RW1, RW1, RW1, RW1, RW1, RW1, WRX, RW1, WRX, RW1, WRX, RW1, WRX, RW1, WRX, RX, R1, RX, RW1, RX, RW1, RX, RW1, RX, RW1, RX, WRX, RX, F0, F1, FRX, FR1, FRX, FW1, FRX, FW1, FRX, FW1, FRX, FW1, FRX, WFX, FRX, RFX, FX ),--RW1 ( U, RZ0, RZ0, RZX, RZ0, RZX, RZX, RW0, RWX, RZ0, RWX, RZ0, RWX, RZX, RWX, RWX, R0, RX, RW0, RX, RZ0, RX, RZ0, RX, RZX, RX, RWX, RX, RX, F0, F1, FR0, RFX, FW0, RFX, FZ0, RFX, FZ0, RFX, FZX, RFX, FWX, RFX, FRX, RFX, FX ),--RZ0 ( U, RZ1, ZRX, RZ1, ZRX, RZ1, ZRX, WRX, RW1, WRX, RZ1, WRX, RZ1, WRX, ZRX, WRX, RX, R1, RX, RW1, RX, RZ1, RX, RZ1, RX, ZRX, RX, WRX, RX, F0, F1, FRX, FR1, FRX, FW1, FRX, FZ1, FRX, FZ1, FRX, ZFX, FRX, WFX, FRX, RFX, FX ),--RZ1 ( U, RDX, RZ0, RZX, RDX, RZX, RZX, RW0, RWX, RZ0, RWX, RDX, RWX, RZX, RWX, RWX, R0, RX, RW0, RX, RZ0, RX, RDX, RX, RZX, RX, RWX, RX, RX, F0, F1, FR0, RFX, FW0, RFX, FZ0, RFX, FDX, RFX, FZX, RFX, FWX, RFX, FRX, RFX, FX ),--RDX ( U, DRX, ZRX, RZ1, ZRX, DRX, ZRX, WRX, RW1, WRX, RZ1, WRX, DRX, WRX, ZRX, WRX, RX, R1, RX, RW1, RX, RZ1, RX, DRX, RX, ZRX, RX, WRX, RX, F0, F1, FRX, FR1, FRX, FW1, FRX, FZ1, FRX, DFX, FRX, ZFX, FRX, WFX, FRX, RFX, FX ),--DRX ( U, RZX, RZX, RZX, RZX, RZX, RZX, RW0, RWX, RZX, RWX, RZX, RWX, RZX, RWX, RWX, R0, RX, RW0, RX, RZX, RX, RZX, RX, RZX, RX, RWX, RX, RX, F0, F1, FR0, RFX, FW0, RFX, FZX, RFX, FZX, RFX, FZX, RFX, FWX, RFX, FRX, RFX, FX ),--RZX ( U, ZRX, ZRX, ZRX, ZRX, ZRX, ZRX, WRX, RW1, WRX, ZRX, WRX, ZRX, WRX, ZRX, WRX, RX, R1, RX, RW1, RX, ZRX, RX, ZRX, RX, ZRX, RX, WRX, RX, F0, F1, FRX, FR1, FRX, FW1, FRX, ZFX, FRX, ZFX, FRX, ZFX, FRX, WFX, FRX, RFX, FX ),--ZRX ( U, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, RWX, R0, RX, RWX, RX, RWX, RX, RWX, RX, RWX, RX, RWX, RX, RX, F0, F1, FR0, RFX, FWX, RFX, FWX, RFX, FWX, RFX, FWX, RFX, FWX, RFX, FRX, RFX, FX ),--RWX ( U, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, WRX, RX, R1, RX, WRX, RX, WRX, RX, WRX, RX, WRX, RX, WRX, RX, F0, F1, FRX, FR1, FRX, WFX, FRX, WFX, FRX, WFX, FRX, WFX, FRX, WFX, FRX, RFX, FX ),--WRX ( U, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, F0, F1, FRX, RFX, FRX, RFX, FRX, RFX, FRX, RFX, FRX, RFX, FRX, RFX, FRX, RFX, FX ),--RX ( U, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, F0, FX, F0, FX, F0, FX, F0, FX, F0, FX, F0, FX, F0, FX, F0, FX, FX ),--F0 ( U, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, F1, FX, F1, FX, F1, FX, F1, FX, F1, FX, F1, FX, F1, FX, F1, FX, F1, FX ),--F1 ( U, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FR0, FRX, FR0, FRX, FR0, FRX, FR0, FRX, FR0, FRX, FR0, FRX, FRX, F0, FX, FR0, FX, FR0, FX, FR0, FX, FR0, FX, FR0, FX, FR0, FX, FRX, FX, FX ),--FR0 ( U, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, FR1, RFX, FR1, RFX, FR1, RFX, FR1, RFX, FR1, RFX, FR1, RFX, FR1, RFX, FX, F1, FX, FR1, FX, FR1, FX, FR1, FX, FR1, FX, FR1, FX, FR1, FX, RFX, FX ),--FR1 ( U, FW0, FW0, FW0, FW0, FW0, FW0, FW0, FWX, FW0, FWX, FW0, FWX, FW0, FWX, FWX, FR0, FRX, FW0, FRX, FW0, FRX, FW0, FRX, FW0, FRX, FWX, FRX, FRX, F0, FX, FR0, FX, FW0, FX, FW0, FX, FW0, FX, FW0, FX, FWX, FX, FRX, FX, FX ),--FW0 ( U, FW1, FW1, FW1, FW1, FW1, FW1, WFX, FW1, WFX, FW1, WFX, FW1, WFX, FW1, WFX, RFX, FR1, RFX, FW1, RFX, FW1, RFX, FW1, RFX, FW1, RFX, WFX, RFX, FX, F1, FX, FR1, FX, FW1, FX, FW1, FX, FW1, FX, FW1, FX, WFX, FX, RFX, FX ),--FW1 ( U, FZ0, FZ0, FZX, FZ0, FZX, FZX, FW0, FWX, FZ0, FWX, FZ0, FWX, FZX, FWX, FWX, FR0, FRX, FW0, FRX, FZ0, FRX, FZ0, FRX, FZX, FRX, FWX, FRX, FRX, F0, FX, FR0, FX, FW0, FX, FZ0, FX, FZ0, FX, FZX, FX, FWX, FX, FRX, FX, FX ),--FZ0 ( U, FZ1, ZFX, FZ1, ZFX, FZ1, ZFX, WFX, FW1, WFX, FZ1, WFX, FZ1, WFX, ZFX, WFX, RFX, FR1, RFX, FW1, RFX, FZ1, RFX, FZ1, RFX, ZFX, RFX, WFX, RFX, FX, F1, FX, FR1, FX, FW1, FX, FZ1, FX, FZ1, FX, ZFX, FX, WFX, FX, RFX, FX ),--FZ1 ( U, FDX, FZ0, FZX, FDX, FZX, FZX, FW0, FWX, FZ0, FWX, FDX, FWX, FZX, FWX, FWX, FR0, FRX, FW0, FRX, FZ0, FRX, FDX, FRX, FZX, FRX, FWX, FRX, FRX, F0, FX, FR0, FX, FW0, FX, FZ0, FX, FDX, FX, FZX, FX, FWX, FX, FRX, FX, FX ),--FDX ( U, DFX, ZFX, FZ1, ZFX, DFX, ZFX, WFX, FW1, WFX, FZ1, WFX, DFX, WFX, ZFX, WFX, RFX, FR1, RFX, FW1, RFX, FZ1, RFX, DFX, RFX, ZFX, RFX, WFX, RFX, FX, F1, FX, FR1, FX, FW1, FX, FZ1, FX, DFX, FX, ZFX, FX, WFX, FX, RFX, FX ),--DFX ( U, FZX, FZX, FZX, FZX, FZX, FZX, FW0, FWX, FZX, FWX, FZX, FWX, FZX, FWX, FWX, FR0, FRX, FW0, FRX, FZX, FRX, FZX, FRX, FZX, FRX, FWX, FRX, FRX, F0, FX, FR0, FX, FW0, FX , FZX, FX , FZX, FX , FZX, FX , FWX, FX , FRX, FX , FX ),--FZX ( U, ZFX, ZFX, ZFX, ZFX, ZFX, ZFX, WFX, FW1, WFX, ZFX, WFX, ZFX, WFX, ZFX, WFX, RFX, FR1, RFX, FW1, RFX, ZFX, RFX, ZFX, RFX, ZFX, RFX, WFX, RFX, FX, F1, FX, FR1, FX , FW1, FX , ZFX, FX , ZFX, FX , ZFX, FX , WFX, FX, RFX, FX ),--ZFX ( U, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FWX, FR0, FRX, FWX, FRX, FWX, FRX, FWX, FRX, FWX, FRX, FWX, FRX, FRX, F0, FX, FR0, FX, FWX, FX , FWX, FX , FWX, FX , FWX, FX , FWX, FX, FRX, FX , FX ),--FWX ( U, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, WFX, RFX, FR1, RFX, WFX, RFX, WFX, RFX, WFX, RFX, WFX, RFX, WFX, RFX, FX, F1, FX, FR1, FX, WFX, FX , WFX, FX , WFX, FX , WFX, FX , WFX, FX, RFX, FX ),--WFX ( U, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, FRX, F0, FX, FRX, FX, FRX, FX , FRX, FX , FRX, FX , FRX, FX , FRX, FX, FRX, FX, FX ),--FRX ( U, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, RFX, FX, F1, FX, RFX, FX, RFX, FX , RFX, FX , RFX, FX , RFX, FX , RFX, FX, RFX, FX ),--RFX ( U, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX, FX )--FX ); END std_logic; --################################################################################## --################################################################################## --################## ################## --################## PACKAGE BODY ################## --################## ################## --################################################################################## --################################################################################## PACKAGE BODY std_logic IS --$ !VANTAGE_METACOMMENTS_ON --$ !VANTAGE_DNA_ON -- *************************************************************************** -- -- FUNCTIONS LOCAL TO THIS PACKAGE. -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- function name: f_max_time -- parameters: -- in t1 -- time -- in t2 -- time -- -- returns: time -- The maximum of the two time values. -- -- purpose: Compute the maximum time value of the two provided. -- ------------------------------------------------------------------------------ FUNCTION f_max_time( t1, t2 : IN time ) RETURN time IS BEGIN IF (t1 > t2) THEN RETURN t1; ELSE RETURN t2; END IF; END f_max_time; -- *************************************************************************** -- -- PUBLIC OVERLOADED COMPARISON OPERATOR FUNCTIONS. -- -- *************************************************************************** -- "=" operator. function "=" ( L : t_logic; R : t_state ) return BOOLEAN is begin return( f_state( L ) = R ); end; function "=" ( L : t_state; R : t_logic ) return BOOLEAN is begin return( L = f_state( R ) ); end; -- "/=" operator. function "/=" ( L : t_logic; R : t_state ) return BOOLEAN is begin return( f_state( L ) /= R ); end; function "/=" ( L : t_state; R : t_logic ) return BOOLEAN is begin return( L /= f_state( R ) ); end; -- "<" operator. function "<" ( L : t_logic; R : t_state ) return BOOLEAN is begin return( f_state( L ) < R ); end; function "<" ( L : t_state; R : t_logic ) return BOOLEAN is begin return( L < f_state( R ) ); end; -- "<=" operator. function "<=" ( L : t_logic; R : t_state ) return BOOLEAN is begin return( f_state( L ) <= R ); end; function "<=" ( L : t_state; R : t_logic ) return BOOLEAN is begin return( L <= f_state( R ) ); end; -- ">" operator. function ">" ( L : t_logic; R : t_state ) return BOOLEAN is begin return( f_state( L ) > R ); end; function ">" ( L : t_state; R : t_logic ) return BOOLEAN is begin return( L > f_state( R ) ); end; -- ">=" operator. function ">=" ( L : t_logic; R : t_state ) return BOOLEAN is begin return( f_state( L ) >= R ); end; function ">=" ( L : t_state; R : t_logic ) return BOOLEAN is begin return( L >= f_state( R ) ); end; -- *************************************************************************** -- -- PUBLICLY AVAILABLE FUNCTIONS. -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- function name: f_logic_bus -- parameters: -- in s -- t_logic_vector -- -- returns: t_logic -- resolved value based on driving values. -- -- purpose: Resolution function for the 38 state value system. -- ------------------------------------------------------------------------------ FUNCTION f_logic_bus( s : t_logic_vector ) RETURN t_logic IS VARIABLE result : t_logic; -- result so far BEGIN -- If no inputs then default is D IF (s'LENGTH = 0) THEN RETURN D; ELSIF (s'LENGTH = 1) THEN RETURN s(s'LOW); -- Calculate value based on inputs ELSE result := D; -- Iterate through all inputs FOR i IN s'LOW TO s'HIGH LOOP if ( s(i) = U ) then return U; end if; if ( s(i) = D ) then NEXT; end if; result := f_busres(result)(s(i)); END LOOP; -- Return the resultant value RETURN result; END IF; END f_logic_bus; -- *************************************************************************** -- -- TIMING UTILITY FUNCTIONS -- -- *************************************************************************** ------------------------------------------------------------------------------ -- -- function name: f_delay -- parameters: -- in newlv -- t_logic -- new logic value -- in delay01 -- time -- 0->1 delay value -- in delay10 -- time -- 1->0 delay value -- -- returns: time -- The appropriate delay to be used. -- -- purpose: Compute the appropriate delay to be used for a transition -- on an output port from either 0 to 1 or 1 to 0. -- ------------------------------------------------------------------------------ FUNCTION f_delay( newlv : IN t_logic; delay01 : IN time; delay10 : IN time) RETURN time IS BEGIN CASE f_state(newlv) IS WHEN '0' => RETURN delay10; WHEN '1' => RETURN delay01; WHEN 'X' => IF (delay01 > delay10) THEN RETURN delay01; ELSE RETURN delay10; END IF; END CASE; END f_delay; ------------------------------------------------------------------------------ -- -- function name: f_zdelay -- parameters: -- in oldlv -- t_logic -- old logic value -- in newlv -- t_logic -- new logic value -- in delay01 -- time -- 0->1 delay value -- in delay10 -- time -- 1->0 delay value -- in delayz0 -- time -- z->0 delay value -- in delayz1 -- time -- z->1 delay value -- in delay0z -- time -- 0->z delay value -- in delay1z -- time -- 1->z delay value -- -- returns: time -- The appropriate delay to be used. -- -- purpose: Compute the delay to schedule for a tristate output based on -- the transistion of the output. If the output is going to a 1 -- from 0 then use the 0->1 delay, which is delay01. If the output -- is going from a 1->z value the use the delay1z value. etc. -- ------------------------------------------------------------------------------ FUNCTION f_zdelay( oldlv : IN t_logic; newlv : IN t_logic; delay01 : IN time; delay10 : IN time; delayz0 : IN time; delayz1 : IN time; delay0z : IN time; delay1z : IN time) RETURN time IS VARIABLE old_strength : t_strength; VARIABLE new_strength : t_strength; BEGIN -- Compute the strengths. old_strength := f_strength( oldlv ); new_strength := f_strength( newlv ); -- If both are 'Z', then take the highest of the four 'z' delays. IF ((old_strength <= 'Z') AND (new_strength <= 'Z')) THEN RETURN( f_max_time( delayz0, f_max_time( delayz1, f_max_time( delay0z, delay1z ) ) ) ); -- If the old strength is 'Z', then it must be delayz?. ELSIF (old_strength <= 'Z') THEN CASE f_state( newlv ) IS WHEN '0' => RETURN delayz0; WHEN '1' => RETURN delayz1; WHEN 'X' => RETURN ( f_max_time( delayz0, delayz1 ) ); END CASE; -- If the new strength is 'Z', then it must be delay?z. ELSIF (new_strength <= 'Z') THEN CASE f_state( oldlv ) IS WHEN '0' => RETURN delay0z; WHEN '1' => RETURN delay1z; WHEN 'X' => RETURN ( f_max_time( delay0z, delay1z ) ); END CASE; -- Otherwise, use f_delay TO compute the delay. ELSE RETURN( f_delay( newlv, delay01, delay10 ) ); END IF; END f_zdelay; ------------------------------------------------------------------------------ -- -- function name: f_convu -- parameters: -- in newval -- t_logic -- new state value (ONLY STATE -- information is used) -- in lastval -- t_logic -- old state value -- in tech -- t_technology -- technology of gate -- -- returns: t_logic -- strongest possible state -- -- purpose: This function calculates the state that should be output -- from a tristateable output when the gating signal is of an -- unknown value. This function basically calculates the -- strongest possible state that this gate could put out. -- ------------------------------------------------------------------------------ FUNCTION f_convu( newval : IN t_logic; lastval : IN t_logic; tech : IN t_technology ) RETURN t_logic IS VARIABLE oldst : t_state; VARIABLE newst : t_state; BEGIN -- Pickup states for values oldst := f_state( lastval ); newst := f_state( newval ); CASE newst IS -- new value is false WHEN '0' => CASE oldst IS -- from false to false WHEN '0' => CASE tech IS WHEN ecl => RETURN RZ0; WHEN cmos =>RETURN FZ0; WHEN nmos =>RETURN FZ0; WHEN ttl => RETURN FZ0; WHEN ttloc => RETURN FZ0; END CASE; -- from true/unknown to false WHEN '1'|'X' => CASE tech IS WHEN ecl => RETURN RZX; WHEN cmos =>RETURN FZX; WHEN nmos =>RETURN FZX; WHEN ttl => RETURN FZX; WHEN ttloc => RETURN FZX; END CASE; END CASE; -- new value is true WHEN '1' => CASE oldst IS -- from true to true WHEN '1' => CASE tech IS WHEN ecl => RETURN FZ1; WHEN cmos =>RETURN FZ1; WHEN nmos =>RETURN RZ1; WHEN ttl => RETURN FZ1; WHEN ttloc => RETURN ZX; END CASE; -- from false/unknown to true WHEN '0'|'X' => CASE tech IS WHEN ecl => RETURN ZFX; WHEN cmos =>RETURN ZFX; WHEN nmos =>RETURN ZRX; WHEN ttl => RETURN ZFX; WHEN ttloc => RETURN ZX; END CASE; END CASE; -- new value is unknown WHEN 'X' => -- from any value to unknown CASE tech IS WHEN ecl => RETURN RFX; WHEN cmos =>RETURN FX; WHEN nmos =>RETURN FRX; WHEN ttl => RETURN FX; WHEN ttloc => RETURN FZX; END CASE; END CASE; END f_convu; ------------------------------------------------------------------------------ -- -- function name: f_convx -- parameters: -- in newval -- t_logic -- new state value (ONLY STATE -- information is used) -- in lastval -- t_logic -- old state value -- in tech -- t_technology -- technology of gate -- -- returns: t_logic -- strongest possible state -- -- purpose: This function calculates the state that should be output -- from a tristateable output when the gating signal is of an -- unknown value. This function basically calculates the -- strongest possible state that this gate could put out. -- ------------------------------------------------------------------------------ FUNCTION f_convx( newval : IN t_logic; lastval : IN t_logic; tech : IN t_technology ) RETURN t_logic IS VARIABLE oldst : t_state; VARIABLE newst : t_state; BEGIN CASE tech IS WHEN ecl => RETURN RFX; WHEN cmos =>RETURN FX; WHEN nmos =>RETURN FRX; WHEN ttl => RETURN FX; WHEN ttloc => RETURN FZX; END CASE; END f_convx; ------------------------------------------------------------------------------ -- -- function name: f_uxfr -- parameters: -- in G -- t_logic -- in Src -- t_logic -- in Drn -- t_logic -- -- returns: t_logic -- to drive Drn output -- -- purpose: This function calculates the output value of Drn based on the -- current values of G, Src, and Drn. -- if G is on then -- the output to Drn is Src -- elsif G is off then -- the output to Drn is f_convz(Drn) -- else -- the output to Drn is the interval between Src and f_convz(Drn) -- end if; -- ------------------------------------------------------------------------------ FUNCTION f_uxfr ( G,Src,Drn : IN t_logic ) RETURN t_logic IS VARIABLE t0,t1: t_logic; VARIABLE s0L,s0H,s1L,s1H,s0M,s1M: t_strength; BEGIN CASE f_state( G ) is WHEN '0' => RETURN f_convz( Drn ); WHEN '1' => RETURN Src; WHEN 'X' => t0 := f_convz( Drn ); t1 := Src; s0L := f_strengthL(t0); s0H := f_strengthH(t0); s1L := f_strengthL(t1); s1H := f_strengthH(t1); IF f_state(t0) = f_state(t1) then IF f_state(t0) = 'X' then IF s0L < s1L then s0L := s1L; END IF; IF s0H < s1H then s0H := s1H; END IF; RETURN f_logicX(s0L)(s0H); else IF s0L > s1L then s0L := s1L; END IF; IF s0H < s1H then s0H := s1H; END IF; IF f_state(t0) = '0' then RETURN f_logic0(s0L)(s0H); else RETURN f_logic1(s0L)(s0H); END IF; END IF; else s0M := t_strength'low; s1M := t_strength'low; CASE f_state(t0) is WHEN '0' => s0M := s0H; WHEN '1' => s1M := s0H; WHEN 'X' => s0M := s0L; s1M := s0H; END CASE; CASE f_state(t1) is WHEN '0' => IF s0M < s1H then s0M := s1H; END IF; WHEN '1' => IF s1M < s1H then s1M := s1H; END IF; WHEN 'X' => IF s0M < s1L then s0M := s1L; END IF; IF s1M < s1H then s1M := s1H; END IF; END CASE; RETURN f_logicX(s0M)(s1M); END IF; END CASE; END f_uxfr; ------------------------------------------------------------------------------ -- -- function name: f_resistor -- parameters: -- in S -- t_logic -- in SIZE -- natural -- -- returns: t_logic -- to drive D output -- -- purpose: This function calculates the output value of D based on the -- current values of S. The strength of S is decreased by SIZE level. -- ------------------------------------------------------------------------------ FUNCTION f_resistor ( S : IN t_logic; SIZE : IN natural ) RETURN t_logic IS VARIABLE sl, sh : t_strength; BEGIN sl := f_strengthL( S ); sh := f_strengthH( S ); if t_strength'pos( sl ) > (t_strength'pos( t_strength'low ) + SIZE) then sl := t_strength'val( t_strength'pos( sl ) - SIZE ); else sl := 'U'; end if; if t_strength'pos( sh ) > (t_strength'pos( t_strength'low ) + SIZE) then sh := t_strength'val( t_strength'pos( sh ) - SIZE ); else sh := 'U'; end if; CASE f_state(S) is WHEN '0' => return f_logic0( sl )( sh ); WHEN '1' => return f_logic1( sl )( sh ); WHEN 'X' => return f_logicX( sl )( sh ); END CASE; END f_resistor; ------------------------------------------------------------------------------ -- -- function name: f_ceil -- parameters: -- in S -- t_logic -- in SIZE -- t_strength -- -- returns: t_logic -- to drive D output -- -- purpose: This function calculates the output value of D based on the -- current values of S. The strength of S is decreased by SIZE level. -- ------------------------------------------------------------------------------ FUNCTION f_ceil ( S : IN t_logic; SIZE : IN t_strength ) RETURN t_logic IS VARIABLE sl, sh : t_strength; BEGIN sl := f_strengthL( S ); sh := f_strengthH( S ); if sl > SIZE then sl := SIZE; end if; if sh > SIZE then sh := SIZE; end if; CASE f_state(S) is WHEN '0' => return f_logic0( sl )( sh ); WHEN '1' => return f_logic1( sl )( sh ); WHEN 'X' => return f_logicX( sl )( sh ); END CASE; END f_ceil; ------------------------------------------------------------------------------ -- -- function name: f_cap -- parameters: -- in S -- t_logic -- in SIZE -- t_strength -- -- returns: t_logic -- to drive D output -- -- purpose: This function implements the capacitor. -- IF the strength of S is larger or equal to the -- size of the capacitor THEN -- RETURN S; -- ELSE -- RETURN the value charged up in the capacitor. -- END IF; -- -- ------------------------------------------------------------------------------ FUNCTION f_cap ( S : IN t_logic; SIZE : IN t_strength ) RETURN t_logic IS VARIABLE sl, sh : t_strength; BEGIN sl := f_strengthL( S ); sh := f_strengthH( S ); if sl < SIZE then sl := SIZE; end if; if sh < SIZE then sh := SIZE; end if; CASE f_state(S) is WHEN '0' => return f_logic0( sl )( sh ); WHEN '1' => return f_logic1( sl )( sh ); WHEN 'X' => return f_logicX( sl )( sh ); END CASE; END f_cap; ------------------------------------------------------------------------------ -- -- function name: f_setup_check -- parameters: -- signal in signal_to_check -- t_logic -- Signal to be checked for -- setup violations. -- in Setup_Constraint -- time -- 'Signal_To_Check' must have -- been stable for at least -- this amount of time. -- -- returns: boolean -- false if setup time on input is too small. -- -- purpose: Checks to see that the setup time is not violated between the -- data and clock inputs. -- -- example: -- -- -- 'Setup' checking on a positive-edge triggered clock. -- setup_check: process( CLK ) -- begin -- -- -- Only perform the assertion after the rising edge. -- if (f_rising_edge( CLK )) then -- -- -- Verify that the setup constraint has not been violated. -- assert( f_setup_check( Signal_To_Check, Setup_Constraint ) ) -- report "Setup check violation on 'Signal_To_Check'." -- severity ERROR; -- end if; -- end process setup_check; -- ------------------------------------------------------------------------------ function f_setup_check( signal Signal_To_Check : in t_logic; Setup_Constraint : in time ) return boolean is begin return (Signal_To_Check'LAST_EVENT >= Setup_Constraint); end f_setup_check; ------------------------------------------------------------------------------ -- -- function name: f_pulse_check -- parameters: -- signal in signal_to_check -- t_logic -- Signal to be checked for -- a minimum pulse width. -- in Minimum_Width -- time -- Minimum width of the -- pulse for this signal. -- -- returns: boolean -- False if pulse width on input is too small. -- -- purpose: Checks to make sure that a pulse on the 'signal_to_check' is not -- narrower than the time specified in width. -- -- example: -- -- -- Positive pulse checking. -- pulse_check: process( CLK ) -- begin -- -- -- Only perform the assertion after the clock falls. -- if (f_falling_edge( CLK )) then -- -- -- Verify that the pulse width constraint has not been violated. -- assert( f_pulse_check( CLK, Minimum_Width ) ) -- report "Pulse check violation on 'CLK'." -- severity ERROR; -- end if; -- end process pulse_check; -- ------------------------------------------------------------------------------ function f_pulse_check( signal Signal_To_Check : in t_logic; Minimum_Width : in time ) return boolean is begin return (Signal_To_Check'LAST_EVENT >= Minimum_Width); end f_pulse_check; ------------------------------------------------------------------------------ -- -- function name: f_hold_check -- parameters: -- signal in signal_to_check -- t_logic -- Signal to be checked for -- Hold violations. -- in hold_time -- time -- Hold time constraint. -- -- returns: boolean -- False if hold time on input is too small. -- -- purpose: Checks to see that the hold time of the input signal is long -- enough compared to the clock input. -- -- -- notes: To use this function properly, you must wait for 'hold_time' -- after the clock pulse and then call this function. -- -- example: -- -- -- Positive-edge triggered hold time checking process. -- hold_check: process( CLK'DELAYED( HoldTime ) ) -- begin -- -- -- Only perform the assertion after the rising edge. -- if (f_rising_edge( CLK'DELAYED( HoldTime ) )) then -- -- -- Verify that the hold constraint has not been violated. -- assert( f_hold_check( Signal_To_Check, HoldTime ) ) -- report "Hold check violation on 'Signal_To_Check'." -- severity ERROR; -- end if; -- end process hold_check; -- ------------------------------------------------------------------------------ function f_hold_check( signal Signal_To_Check : in t_logic; Hold_Time : in time ) return boolean is begin return (Signal_To_Check'LAST_EVENT >= Hold_Time ); end f_hold_check; END std_logic;