-------------------------------------------------------------------------------
--
--   Project     :  ATEP
--   File name   :  uartrx.vhd
--   Title       :  UART Receiver 
--   Description :  UART receiver  selection
--
-------------------------------------------------------------------------------
--   Revisions   :
--          Date                Author          Revision        Comments
-- Sat Oct 30 10:05:49 1994     cohen   Rev A           Creation
-------------------------------------------------------------------------------
entity UartRx_Nty is
  port (Clk16xT       : in      bit;
        ResetF        : in      bit;
        Serial_InT    : in      bit;
        DataRdyT      : out     boolean;
        DataOuT       : out     Bit_Vector(7 downto 0);
        BitClkT       : out     bit);
end UartRx_Nty;


architecture UartRx_Beh of UartRx_Nty is
  subtype Int0to15_Typ is integer range 0 to 15;
  constant RxInit_c : Bit_Vector(9 downto 0) := "1111111111";
  signal RxReg_s   : Bit_Vector(9 downto 0); -- the receive  register
  signal Count16_s : Int0to15_Typ;            --  for divide by 16
  signal RxMT_s    : boolean;            --   Receive register empty
  signal RxIn_s    : bit;                --   registered serial input
  
  
begin  --  UartRx_Beh 
  -----------------------------------------------------------------------------
  --  Process:   Xmit_Lbl
  --  Purpose:   Models the receive portion of a UART.
  --             Operation is as follows:
  --             
  --             
  --             
  --             
  --             
  --             
  --             
  --             
  --             
  --             
  --             
  --             
  --            
  -----------------------------------------------------------------------------
  Rx_Lbl : process
  
  begin  --  process Rx_Lbl
     wait until Clk16xT'event and Clk16xT = '1';
     --   Clock serial input into RxIn_s
     RxIn_s <= Serial_InT;
        
     --   reset
     if (ResetF = '0') then
       Count16_s <= 0;                   --   reset divide by 16 counter
       RxMT_s <= true;                    --   new message starting
       RxReg_s <= RxInit_c;
     
     --   new bit start   
     elsif (RxMT_s and RxIn_s = '0') then
       Count16_s <= 0;                   --   reset divide by 16 counter
       RxMT_s <= false;                    --   new message starting
       RxReg_s <= RxInit_c;
     
     --   If in a receive transaction mode
     --   if @ mid bit clock then clock data into register
     elsif Count16_s = 7  and not RxMT_s then --   mid clock
       RxReg_s <= RxIn_s & RxReg_s(9 downto 1);
       Count16_s <= Count16_s + 1;
     
     --   if @ 16X clock rollover
     elsif Count16_s = 15 then 
       Count16_s <= 0;
     
     --   Normal count16 counter increment
     else 
       Count16_s <= Count16_s + 1;
     end if;


     --   Check if a data word is received
     if not RxMT_s and RxReg_s(9) = '1' and RxReg_s(0) = '0' then 
       DataRdyT <= true;
       RxMT_s <= true;
     else
       DataRdyT <= false;
     end if;
  end process Rx_Lbl;

-------------------------------------------------------------------------------
--  Concurrent signal assignment for BitClkT and DataOut
-------------------------------------------------------------------------------
  BitClkT <=      '1' when Count16_s = 9
             else '0';

  DataOuT <= RxReg_s(8 downto 1);

end UartRx_Beh;