-----------------------------------------------------------------------
-- package with component declarations
------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
--
package gates_PKG is

    component andg
        generic (tpd_hl : time;
                 tpd_lh : time);
        port (in1, in2 : std_logic;    
              out1 : out std_logic);
    end component;  

    component org
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1, in2 : std_logic;
               out1 : out std_logic);
    end component;  
    
    component xorg
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1, in2 : std_logic;
               out1 : out std_logic);
    end component;  

    component xnorg
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1, in2 : std_logic;
               out1 : out std_logic);
    end component;  
    
    component nandg
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1, in2 : std_logic;
               out1 : out std_logic);
    end component;  

    component norg
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1, in2 : std_logic;
               out1 : out std_logic);
    end component;  

    component invg
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1 : std_logic;
               out1 : out std_logic);
    end component;  

    component buffg
         generic (tpd_hl : time;
                  tpd_lh : time);
         port (in1 : std_logic;
               out1 : out std_logic);
    end component;  

-- ******* Portes generiques sur le nombre d'entr‚e
  
    component andg_n 
            generic (n      : integer ;
                     tpd_hl : time ;
                     tpd_lh : time);
            port (inp : std_logic_vector(0 to n-1);
                  out1 : out std_logic) ;
    end component;              

    component nandg_n 
            generic (n      : integer ;
                     tpd_hl : time ;
                     tpd_lh : time );
            port (inp : std_logic_vector(0 to n-1);
                  out1 : out std_logic) ;
    end component;              

    component org_n 
            generic (n      : integer ;
                     tpd_hl : time ;
                     tpd_lh : time) ;
            port (inp : std_logic_vector(0 to n-1);
                  out1 : out std_logic) ;
    end component;              
    
    component norg_n 
            generic (n      : integer ;
                     tpd_hl : time ;
                     tpd_lh : time) ;
            port (inp : std_logic_vector(0 to n-1);
                  out1 : out std_logic) ;
    end component;              

    component xorg_n 
            generic (n      : integer ;
                     tpd_hl : time ;
                     tpd_lh : time) ;
            port (inp : std_logic_vector(0 to n-1);
                  out1 : out std_logic) ;
    end component;              

    component xnorg_n 
            generic (n      : integer ;
                     tpd_hl : time ;
                     tpd_lh : time) ;
            port (inp : std_logic_vector(0 to n-1);
                  out1 : out std_logic) ;
    end component;              

end gates_PKG;