***************************************************** ** ** ** BENCHMARKS FOR VHDL SIMULATION ** ** ** ** ISCAS85 / ISCAS 89 Translation ** ** ** ** Yannick HERVE/Francois PECHEUX 10/01/94 ** ** ** ***************************************************** This set is a VHDL translation of ISCAS85 and ISCAS89 netlist based benchmarks. Original benchmarks are on ftp/anonymous server at mcnc.mcnc.org in pub/benchmark/ISCAS85 and pub/benchmark/ISCAS89 directories (december 1993 version). Benchmarks are available in VHDL at structural and RTL level. Netlists have been automatically re-write in VHDL. For ISCAS89,a clock has been added. **************************************** ******** BENCHMARK LIST ********** **************************************** Total: 65 benchmarks ****** Glossaire ************ #gates : number of gatess #deep : combinatorial circuits deep #in : number of primary inputs #out : number of output #sign : internal signals number (out of in and out) Su : intrinsic concurrency crit.path : * : value under processing *-- In the database --- not yet in the database ************************************************ ****** combinatorial circuits of ISCAS'85 ****** ************************************************ ISCAS'85 # gates #deep #in #out #sign Su (first list: 11 circuits) *-- C17 6 3 5 2 4 * *-- C432 160 * 36 7 153 * *-- C499 202 * 41 32 170 * *-- C880 383 * 60 26 357 * *-- C1355 546 * 41 32 514 * *-- C1908 877 * 33 25 855 * --- C2670 1269 * 243 140 1129 * *-- C3540 1669 * 50 22 1647 * *-- C5315 2307 * 178 123 2184 * *-- C6288 2416 * 32 32 2384 * *-- C7552 3513 * 207 108 3405 * ISCAS'85 # gates #deep #in #out #sign Su (no-redundancy: 9 circuits) *-- C432.nr *-- C499.nr *-- C1355.nr *-- C1908.nr --- C2670.nr *-- C3540.nr *-- C5315.nr under report *-- C6288.nr *-- C7552.nr ********************************************** ****** sequential circuits of ISCAS'89 ****** ********************************************** ISCAS'89 # gates #fl.flop crit.path #in #out #sign Su (first list: 31 circuits) *-- s27 11 3 5 4 1 11 6.3 *-- s208-1 104 8 * 10 1 111 18 *-- s298 119 14 * 3 6 127 28 *-- s344 160 15 * 9 11 164 * *-- s349 161 15 * 9 11 165 * *-- s382 158 21 * 3 6 173 * *-- s386 159 6 * 7 7 128 * *-- s400 164 21 * 3 6 179 * *-- s420-1 218 16 * 18 1 233 * *-- s444 181 21 * 3 6 196 * *-- s510 211 6 * 19 7 210 * *-- s526n 194 21 * 3 6 209 * *-- s641 379 19 * 35 24 374 * *-- s713 393 19 * 35 23 389 37.6 *-- s820 289 5 * 18 19 275 * --- s832 287 5 * 18 19 273 * *-- s838-1 446 32 * 34 1 477 * --- s953 395 29 * 16 23 401 * *-- s1196 529 18 * 14 14 533 * *-- s1238 508 18 * 14 14 512 * *-- s1423 657 74 * 17 5 726 * *-- s1488 653 6 * 8 19 640 * *-- s1494 647 6 * 8 19 634 * *-- s5378 2779 179 * 35 49 2909 * --- s9234-1 5597 211 * 36 39 5769 * --- s13207-1 7951 638 * 62 152 8437 * --- s15850-1 9772 534 * 77 150 10156 * --- --- s35932 16065 1728 * 35 320 17473 * --- s38417 22179 1636 * 28 106 23709 * --- s38584-1 19253 1426 * 38 304 20375 * ISCAS'89 # gates #fl.flop crit.path #in #out #sign Su (addendum: 15 circuits) --- s344 160 15 * 9 11 164 * --- s499 152 22 * 1 22 152 * --- s635 286 32 * 2 1 317 * --- s938 446 32 * 34 1 477 * --- s967 394 29 * 16 23 400 * --- s991 519 19 * 65 17 521 * --- s1196 529 18 * 14 14 533 * --- s1269 569 37 * 18 10 596 * --- s1512 780 57 * 29 21 816 * --- s3271 1572 116 * 26 14 1674 * --- s3330 1789 132 * 40 73 1848 * --- s3384 1685 183 * 43 26 1842 * --- s4863 2342 104 * 49 16 2430 * --- s6669 3080 239 * 83 55 3264 * --- prolog 1601 136 * 36 73 1664 *