PPT Slide
Not a clear winner between FSM and uCode for Xilinx
Clever use of machine cycles could reduce average microcode words per opcode
Vertical encoding of datapath signals could reduce uCode width (could also reduce gate count in FSM as well)
uCode versus FSM tradeoffs is technology dependent.
What about other FPGA technologies besides Xilinx?
Ucode would give more predictable delay path for control.
Further investigation may be warranted.
Would Microcode Reduce Control Size? (cont.)