Synthesis Tweaking

• RFCORE for Xilinx used 1 FF per bit (16x16 bits)

  • 128 CLBs for storage, rest for decoding
  • If X4000E DPRAM (1 write port, 2 read ports), RFCORE < 50 CLBs

• Decode/Constant blocks basically ROMs, CLB count can be lower if ROM capability used.

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