A Synthesizeable VHDL Model of the 1750A Integer Subset
Introduction
Presentation Outline
Goals
Environment
Mil-Spec-1750A
1750A (cont.)
Fairchild F9450
1750A VHDL Model
Model Bus Diagram
Register Definitions
Entity Hierarchy
Comments on Model Hierarchy
Control Block Diagram
Comments on Control
Comments on Control (cont.)
Model Testing
SEAFAC Tests
Regression Test System
Regression Test Results
Sample Execution Times
Synthesis Cell/CLB Counts
Comments on Synthesis Results
Comments on Synthesis (cont)
Synthesis Tweaking
Synthesis Tweaking (cont.)
What is Left?
Project CLB Counts if FP Added
Would Microcode Approach Reduce CLB Count?
Would Microcode ... (cont.)
In Closing
Email: reese@erc.msstate.edu
Home Page: http://www.erc.msstate.edu/mpl
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