The experiments described here were made using the Xilinx XC4000 FPGA series [Xil94a]. We have chosen this architecture mainly for tool and support availability, but also because they are a very versatile and advanced FPGA technology.
The data presented here were collected using the Synopsys VHDL design analyzer/FPGA compiler (versions 3.1a--3.3a) [Syn95a] [Syn95e] [Syn95b], the XSI Xilinx/Synopsys interface [Xil94d] and X-BLOX as cell generator (XACT 5.1). Synopsys synthesis and XACT were targeted at a Xilinx XC4013mq240-5 FPGA. For low-level operations, we use the XACT and Viewlogic/Powerview tools for analysis and simulation [Xil94b], [Vie94].
The code for various test circuits was written in VHDL, using the IEEE Std_Logic_1164 package [IEE93]. This package is used in most new VHDL synthesis tools and ensures code portability between tools from different vendors. The synthesis syntax for a given function block may also depend on the tool. The syntax given in this paper was tested using the Synopsys Design Analyzer.
The underlying optimizations described here are not restricted to a particular source code format. Thus, they are not restricted to VHDL, but apply equally well to other hardware description languages such as Verilog [TM91], [SST90]. In fact, many synthesis tools are independent of the source language and have front-ends for both VHDL and Verilog, as well as other special-purpose formats for lookup tables, state machines, etc.
The initial structure of synthesized logic is directly inferred from the structure of the hardware description. Thus, the quality of the final hardware very much depends on the description style used at a higher level. To account for this , the high-level description has to be adapted to guide the synthesis tool to choose the appropriate implementation. This is especially important to exploit special-purpose features such as fast carry logic available in many architectures.