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Up: A VHDL
Methodology for Previous: References
A VHDL Methodology for FPGAs
This work is published in the Proceedings of the European Design and Test Conference ED&TC'96 , Paris, France, March 1996.
This document was generated using the LaTeX2HTML translator Version 95 (Thu Jan 19 1995) Copyright © 1993, 1994, Nikos Drakos, Computer Based Learning Unit, University of Leeds.
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latex2html -contents_in_navigation -no_reuse
-bottom_navigation vhdl4fpga.tex.
The translation was initiated by Michael Gschwind on Tue Sep
26 13:37:06 MET 1995
Up: A VHDL
Methodology for Previous: References