; Xilinx APR Constraints File ; These block names should match the port names in the top level ; VHDL module ; Pads connected to bidirectional Buffer Module local bus place block DATA<0> P72; place block DATA<1> P53; place block DATA<2> P56; place block DATA<3> P58; place block DATA<4> P59; place block DATA<5> P60; place block DATA<6> P61; place block DATA<7> P62; place block DATA<8> P63; place block DATA<9> P65; place block DATA<10> P66; place block DATA<11> P67; place block DATA<12> P68; place block DATA<13> P69; place block DATA<14> P70; place block DATA<15> P71; ; Pads connected to active low SRAM control lines place block MEM_RW P8; place block MEM_OE P9; place block MEM_CE P10; ; Pads connected to bidirectional SRAM data lines ; Note that arbitrary placement among these lines is possible ; which should simplify APR's routing job allow block MEM<0> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<1> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<2> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<3> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<4> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<5> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<6> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<7> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<8> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<9> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<10> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<11> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<12> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<13> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<14> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM<15> P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; ; Pads connected to the SRAM address lines ; These may also be placed arbitrarily among the given set allow block ADDR<0> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<1> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<2> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<3> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<4> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<5> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<6> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<7> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<8> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<9> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<10> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<11> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<12> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<13> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR<14> P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; ; Input pads connected to signals provided by Bullwinkle GAL control logic place block EXTRACT P35; place block TRIGGER P40; place block CHIP_SELECT P46; ; Output pads connected to Bullwinkle control logic or to PC input port place block ALMOST_FULL P39; place block EMPTY P45; place block FULL P47; ; This pad is shared with the configuration signal Init ; and is sampled by the PC input port place block DEBUG P42;