F.2 natasha.v

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-- N A T A S H A . V
-- $Id: natasha.v,v 1.2 1995/04/25 06:48:46 sharring Exp $
-- Scott Harrington
-- Duke EE Project Spring/Fall 1994
-- Address Tracing System
--
-- Natasha provides a simple interface between Boris and the
-- SRAM implementation (currently two 32k x 8 SRAMs).  Natasha
-- uses the trigger and mode information from Boris to produce
-- WE, CE, and OE control signals for the SRAM.
--
-- Refer to Xilinx Prog Logic Data Book p. 8-104
----------------------------------------------------------------

-----------------------
-- I/O descriptions: --
-----------------------

--  Clk: Boris clock
--  Trig: Trigger synched to CLK
--  Ext: extract/record mode of Bullwinkle synched to CLK
--  WE: active low write enable
--  CE: active low chip enable
--  OE: active low output enable

ENTITY natasha IS
    PORT (
        Clk: IN vlbit;
        Trig: IN vlbit;
        Ext: IN vlbit;
        CS: IN vlbit;
        WE: OUT vlbit;
        CE: OUT vlbit;
        OE: OUT vlbit
        );
END natasha;

ARCHITECTURE behav OF natasha IS

BEGIN

    WE <= NOT (Trig AND (NOT Ext));

    CE <= NOT CS;

    OE <= NOT Ext;

END behav;