The construction and testing of the Rocky card and staller software was completed during the Spring 94 semester. In addition, some progress was made toward the design of the FPGA program in VHDL and gaining familiarity with the simulation and synthesis tools described in Appendix A.
During the Fall 94 semester, design of the Bullwinkle control logic and Boris and Natasha VHDL modules was completed. The control GALs were tested in simulation as well as on the card. The VHDL modules were not successfully simulated except for the address pointers module. For preliminary hardware testing purposes, the top-level Boris design was modified to output the pointer values instead of memory values, so that correct operation of the pointers might be ascertained even without the memory interface working.
The Bullwinkle card was constructed and tested with one FPGA module. The physical construction of the board (excepting the three additional buffer modules) is complete. Correct operation of the control logic was observed, and many different Xilinx bit files have been successfully downloaded to the FPGA. The FPGA designs include not only the natasha Address Tracing System design, but also a Fast Circle Generator algorithm, xcircle to demonstrate the general purpose usefulness of the Bullwinkle architecture.
These designs were actually not coded in VHDL, but rather described structurally using the Viewdraw schematic editor. License availability problems with Synopsys forced this change.
Work which remains includes primarily the recording control software, and testing the system with two computers at normal speeds (with a hard disk attached). Initial tests with the ribbon cable indicate no problems with ringing or synchronization. However, more extensive tests should be done and traces compared with expected results.
Finally, the Address Tracing System should be used to generate actual address traces for PC applications. These traces will be annotated and stored on networked machines for easy access.