The sequence of bus signal transitions is similar for memory reads, memory writes, I/O reads, and I/O writes. All four types of cycles can be generated by either CPU traffic or DMA traffic. We are only interested in those addresses generated by the CPU, so we require the AEN signal to be low.
All memory and I/O reads and writes require at least two CPU clock cycles. In the second half of the first cycle the ALE (address latch enable) signal is high. After the first complete cycle (and for one or more clock cycles depending on memory speed) one of the following signals goes low: MEMR, MEMW, IOR, IOW. A simple combinational detector cannot be used because ALE precedes these signals by one-half clock cycle. A flip flop Q1 in the GAL is therefore used. Q1 is asynchronously set to 0 by ALE being high. It is set to 1 with each falling edge of the system clock, that is, midway through each clock cycle. Thus Q1 follows ALE, extended one-half clock cycle, and inverted, so that its rising edge occurs while MEMR, etc. are active.
For the purposes of the address reference counting hardware, a GAL is used which provides a Count Enable signal when MEMR or MEMW is low, and a Count Reset signal when IOW is low and the address decodes to 0x300. These signals control the array of 74LS169 counter chips, along with the pulse from Q1 which triggers either the increment or the reset. Refer to Appendix E.1 for the listing of busmon.abl, the ABEL source for the GAL.