Synthesis Details

Your VHDL modules for synthesis should use the STD_LOGIC and STD_LOGIC_VECTOR data types found in the IEEE library for all signals, variables, and ports. The built-in resolution functions for these types allow bidirectional and multiply-driven signals without confusing conversion functions.

A common requirement for FPGA projects is to have pads that are bidirectional. The schematic representation is shown, and demonstrates that the input is always active and the output is three-state. Inferring the same structure is difficult using VHDL. An example which uses structural VHDL and actually instantiates IBUF and OBUF components can be found in /opt/digital/share/xilinx3/xact/ \ examples/synopsys/dc/xc3000/vhd/bidi_reg.

One additional point of note about I/O pads is the mapping of logic into Xilinx IOBs. Using the flip-flops and function generators present in IOBs conserves valuable CLB resources. Synopsys will automatically map to IOBs if the insert_pads command precedes the compile command.

Synopsys infers clocked devices (flip-flops) from VHDL processes that have statements such as WAIT UNTIL Clk'EVENT AND Clk='1'; or IF (Clk'EVENT AND Clk='1') THEN.... Within such processes, it can infer synchronous and asynchronous clear and preset inputs which are available on the target Xilinx CLB flip-flops.

The Xilinx CLB flip-flops also feature a clock enable (CE) input, which previous version of Synopsys could not properly use by inference. Starting with verson 3.1, however, you can infer clock-enabled flip-flops as shown in the LFSR counter module lfsr.vhd. Clock enable lines allow you to save a lot of feedback combinational logic and prevent the need for gated clocks.

When a flip-flop is inferred, Synopsys traces back the signal that is connected to the flip-flop's clock input to see what port the signal originated from. In an attempt to minimize skew, Synopsys assigns all such clock ports to the FPGA's primary or secondary global clock buffer resources (TCLK or ACLK on the XC3000, BUFGP or BUFGS on the XC4000). Synopsys does not know that the Xilinx parts only have 1 to 4 global clock buffers, and the XNFPREP program will then report errors. The fix to this problem is to specify in your dc_shell script that some of the ports which drive flip-flop clock inputs should not be clocks with the command set_pad_type -no_clock PORTNAME. This is demonstrated in the example project in /opt/digital/share/xilinx3/xact/examples/synopsys/dc/xc3000/vhd/gate_clock.