Before you do any architecture-specific mapping (Synopsys), it is a good idea to do a logic-level simulation of your VHDL code. You should make appropriate revisions to your code at this stage if the logic is not right, because performing the synthesis and mapping steps takes lot of time.
Simulation at this point does not take into account various routing and gate delays that are determined by the FPGA mapping software later.
Many programs exist which read VHDL and perform logic-level simulation. Most digital design students at Duke are familiar with ViewSim.
In ViewSim you can control inputs and display outputs directly or from commands in a .cmd file (see sample lfsr.cmd file). An alternate way of exercising your design is to create a VHDL "test bench" module which instantiates your project as a COMPONENT and feeds various test vectors to its inputs.