[Duke Shield] Duke Department of Electrical Engineering

FPGA Synthesis at Duke

Abstract: This tutorial describes the process of creating a working FPGA design from VHDL. Synopsys VHDL synthesis tools are used, along with Xilinx software which works with Synopsys for Xilinx XC3000 and XC4000 series FPGAs. Simulation can be performed using either Synopsys or Viewlogic simulation tools. At many points in the tutorial text are hypertext links to relevant parts of a sample project.

  • Introduction
  • Do I need to read this tutorial?
  • BORG, GERM, or custom hardware?
  • VHDL Nuances: Simulation vs. Synthesis
  • Where to look for more information

    • That's nice, but get to the point.

  • Setting up your environment for Synopsys and Xilinx tools
  • Planning your FPGA design
  • Simulating your VHDL code
  • Step-by-step instructions, Viewdraw to FPGA
  • Step-by-step instructions, VHDL to FPGA
  • Simulating the placed and routed design
  • VHDL Synthesis Details
  • Summary of commands and effects

    • Sample projects:

  • LFSR Counter (VHDL to GERM)
  • Address Tracing System (ABEL/VHDL/Schematic to custom hardware)

    • Links to other sites:

  • Duke Electrical Engineering Online Documentation
  • VHDL Tid-Bits and Links
  • Synopsys Home Page
  • Xilinx Home Page

    • Created by Scott E. Harrington, Duke Electrical Engineering