This is not a VHDL tutorial, although some language issues are discussed relating to FPGA design and the Synopsys and Viewlogic VHDL tools specifically (see VHDL Nuances). The VHDL code available in the sample projects is a good starting point for learning some basic VHDL constructs. However, you will probably need additional help if you've never used VHDL before.
You may decide that your FPGA design would be easier to describe using a schematic editor instead of a hardware description language. For example, in Powerview, you can use Viewdraw to wire together Xilinx IO block and pad components with macro components such as gates, registers, multiplexors. For this type of design, first read the LaTeX document Powerview_to_FPGA available under /opt/digital/share/tutorials as a DVI file or Postscript file. If you are not familiar with Powerview, there is also a Powerview_tutorial in DVI or Postscript format.
It is also possible to create designs that have some modules drawn in a schematic editor and some written in VHDL or Verilog.
If you think that your FPGA design has components that are best described by a behavioral hardware description such as VHDL, you should read this tutorial. There are many programs, libraries, versions, and file formats involved in the process of creating simulation files and download files from VHDL. These are difficult to piece together correctly simply by trial-and-error (most engineers' favorite method of learning new CAD tools). However, experimentation is strongly encouraged. You can discover many possibilities that the software provides, beyond the limited cross-section of the tools that the tutorial addresses.