Procedural Modeling

USE: High level specification of behavior

entity traffic_light_controller
        generic ( yellow_time : time;
                        min_hwygreen : time;
                        max_hwyred : time );
        port ( farmroad_trip : in boolean;
                  farmroad_light : out color;
                  highway_light : out color
                );
        end traffic_light_controller;

architecture specification of traffic_light_controller is begin

cycle:  process
        begin
highway_light <= green;
farmroad_light <= red;
wait for min_green;
wait  until farmroad_trip;

highway_light <= yellow;
wait for yellow_time;

highway_light <= red;
farmroad_light <= green;
wait until not farmroad_trip for max_hwyred;

        farmroad_light <= yellow;
        wait for yellow_time;
   end process;
end specification;

USE: Detailed Modeling of Behavior

Example: Timed Behavior of Primitive Elements

AND_n:  process (x)
        variable Zvar : bit := '1';
        begin
                for i in x'range loop
                        if x = '0' then
                                Zvar := '0' ;
                                exit ; 
                        end if;
                end loop;
                Z <= Zvar after Tprop ;
        end process AND_n;

Process Statement

Inside a process is a sequential routine to compute the behavior desired for the design at a specific moment in time.

 

label: process
declarations

 begin

 sequential statements

 (typically ended by a wait statement)

 end processlabel ;

 

The model for a process calls for it to be executed once (i.e. at TIME = 0), running till it hits a WAIT statement. Time then advances until the wait condition is satisfied, then execution resumes.

The process body executes in an endless loop, interrupted only by WAIT statements; the bottom of the process contains an implicit "go to the top."

A Concurrent Statement

A process -- declarations, sequential body, and all -- is just another kind of concurrent statement.

Evaluation of a process is caused when one of a list of signals in the wait statement changes value --just as evaluation of a concurrent signal assignment is caused by the change of a value in a condition, select_expression, or waveform.

Just because a process is sequential does NOT mean it is modelling the sequential behavior of a design.

 
 Note that the AND_n process example is the model of a combinational logic element.

TIME DOES NOT ADVANCE within a process; it advances during a WAIT statement.

 

Initialization

Signals, variables, ports can all be set to default values:
 
signal enable : bit := 0;

variable Fval : std_logic  := '0';
 

 As long as Tprop, K, load are generics or constants, we can write
 
 variable Tplh : Time := Tprop + K * load ;
 
Ports can be initialized by
 
entity xyz port ( a : in bit := '0'; . . . )
 
 Even so, this is not enough to fulfill all the requirements for initializing a model.

 



 

At initialization, the user could be expected to provide the value for VVRL, a machine state. For any of the inputs which are primary, initial values can also be required. Inputs which come from other processes may not be initialized. Moreover, it should not be necessary for the designer to compute the initial output values for VVOS and PMRS in the circuit above. Instead, we write for machine evaluation:
 

VVOS <= (not VVRL) and PMR) nor (IOS nand VVRL);
PMRS <= IOS or (( not VVRL) and PMR ) ;
 
By providing initial activation of every process in a VHDL model at TIME = 0, it is possible to write the model so the consequences of setting initial values will be completely propagated. Within a process sequential signal assignment statements are always executed when they are encountered, not just when a signal on the right hand side changes.
 

Variable and signal assignment

Variables: Exist only within procedural bodies, like processes, functions, and procedures. Variable assignment statements appear as follows:  var := expression;

 Variables are used within the sequential body just as in other procedural languages.

 Signals are used to communicate between concurrently executing processes. Within a process they continue to have the form

 sig <= waveform ;

 which means that for the signal a sequence of value updating events is to be scheduled for the future.

 Misuse of Sequential Signal Assignments

 



Note that a signal does not take on its new value until time advances. Until the process hits a WAIT statement, simulation time does not advance, so the signal will never be updated before the WAIT, and may not be updated even after the WAIT is complete if the WAIT completed faster than the signal update.
 

Wait Statements

 wait on signal_list ;
 
The signal_list is also called the sensitivity list . The process will resume execution whenever an event occurs on one of those signals.
 
wait until condition ;

The condition will be evaluated whenever one of the signals in that boolean expression changes value, but execution of the process does not resume until the condition evaluates TRUE.
 wait for time_expression ;

The time_expression represents the time interval before execution of the process resumes. Note that time_expression is not absolute time, but time relative to the time at which the current execution of the process took place.
 Combining these forms permits the creation of complex criteria for process resumption:

wait on DAV for Timeout ;

The process will resume either when DAV changes or until the Timeout delay has occurred. Timeout is effectively a maximum delay till the process resumes.
 wait on a1, a2, a3 until enable = '1'

The process resumes when a change occurs on a1, a2, or a3 and the condition enable = '1' is true. "Until" is misleading here because enable has to actually be high when the change occurs on a1, a2, or a3, to make the process resume.
 

Signals combined with Wait statements give the ability to create communicating sequential processes.  However, synthesis tools do not usually allow the use of multiple WAIT statements within a process, and their use is usually restricted to modeling either combinational logic or clocked sequential circuits.

Example: CPU and Memory handshaking

Memory:  process
        begin
                DAV <= '0';
                wait until Mem_Req = '1';
                Data <= ROM_DATA(Address) after 50 ns;
                DAV <= '1' after 60 ns;
                wait until Mem_Req = '0';
        end process;

CPU_Read:  process
        begin
                Mem_Req <= '0';
                wait until ... the need for memory read  ;
                Address <=  . . . address value . . .
                Mem_Req <= '1' after 10 ns;
                wait until DAV = '1';
                MD_Reg <= Data;
        end process;

Are equivalent to a single WAIT with a sensitivity list at the bottom of the process.  You are likely to see them because this is often the only kind of WAIT statement that synthesis tools are willing to accept.

 The form
 
process
begin
.
.
.
wait on a, b, c, d;
end process;
 
can be replaced with the process header form:
 
myproc: process ( a, b, c, d )
begin
where signals a, b, c, d are the sensitivity list. Whenever any of these signals change value, the process will be executed.
 
Note: Processes with a sensitivity list may not contain any wait statements, nor may they call procedures with wait statements.

Rev. 2/17/98 B. Huey