Data Modeling

OPERATIONS

Primitive Operators

• Logical Operators -- on Boolean and Bit

 

        and     or      nand    nor     xor     not

• Arithmetic Operators

on Integer

        +       -       *       /       mod     rem     abs
        **      (integer power)

on Real and Physical

        +       -       *       /       abs
        **      (integer power)

• Relational Operators

        =       /=                      work on any type

        <       <=      >       >=      any scalar type

• Concatenation -- on Arrays

        &       Note the deceptive meaning of this symbol!!!

Type Conversion

VHDL is a strongly typed language. Conversions between types of objects must be explicit. Requiring explicit conversion nearly always improves the precision of documentation, and frequently helps to avoid subtle errors either in design or modelling.

Explicit type conversion is handled by

target_type ' ( expression )

and is permitted when the types are said to be "closely related." This means approximately that they either are numeric types, or that they share the same base type if they are subtypes. Arrays must have the same dimensionality, but not necessarily the same dimensions.

Examples on numbers:

real'( intval ) converts an integer to real.
integer'( x )   rounds the real value of x to the nearest integer.
natural'( x )   checks to see that the value of x is non-negative (reporting the error if it occurs) and rounds to the nearest integer

An Application using type conversion on arrays:

        signal databyte : byte_int ;
        signal accum    : word_int ;

        -  -  -  -

        accum <= databyte ;                     WRONG!!

        accum <= word_int ( databyte ) ;        OK!!

Operations on Arrays

Slicing

Form
array_name (slice_range )
When a slice appears on the left hand side of an assignment, it is analogous to inserting data into a field of a register.

When a slice is referenced, it is analogous to extracting data from a field of a register.

Example:

                abus <= ax ( 15 downto 8 );

                abus <= ax (  7 downto 0 );

Note: Behavioral models which involve multiplexing "wide" values onto "narrow" buses make this capability essential.

Concatenation

. . . connects arrays end-to-end to make bigger arrays.
It is typically used on one-dimensional vectors to put fields of registers or buses together.

It is also useful for modelling shift and rotate operations.

Examples

AX <= AX ( 14 downto 0 ) & '0'; -- Left shift, zero fill on right end
AX <= AX(0) & AX(15 downto 1);  -- Right rotate

Signal Attributes

Event related attributes

These are the most important of the attribute functions on signals.

S'DELAYED(T)

produces a signal whose waveform has been delayed by T time. Can be used to model delay continuously -- as in a delay line or bus where the effect of bus length is being modelled.

S'STABLE(T)

produces a boolean signal which becomes true at time T after the last change of value on signal S, and changes to false again as soon as the value on S changes again.

Used for checking setup and hold times. If T is the setup time, this will be true at the clocking time. It imposes a fairly high overhead, and should usually be avoided. See the use of S'LAST_EVENT below.

S'EVENT

is a signal whose value is true at exactly the event time when signal S changes value, and false otherwise.

Used to model the clock transition in flipflops.

Example: Up_edge := S'event and S = '1'.

 

S'LAST_EVENT

returns the length of time which has elapsed since the last change on S.

Can be used to compute time-varying values like capacitive dischange in a memory cell at refresh. Is the preferred way to check signal stabilization: J'last_event > Tsetup.

Transaction related signal attributes

When you compute a new value for a signal, a transaction is created. Only if the transaction actually causes the signal to change value when the new value is assigned to the signal does an event occur.

For example, if the evaluation of an OR expression produced a '1' for the new output value in response to input X changing to '1', that transaction would be queued for the simulator. However, the OR gate value may already be '1' (due to the Y input already being '1', or the signal may have other drivers that have forced the value to '1', so that when it comes time to update the signal no change occurs. At this point a transaction has occurred, but no event has occurred. Since no change occurred, this action will not trigger the execution of concurrent signal assignment statements or processes.

In most cases you should be using the EVENT based attributes discussed above, not the TRANSACTION based attributes discussed in this section. These attributes can be useful in studying how much signal activity there is in the design, and can be used to model such things as power use in switching devices.

S'QUIET(T)

produces a boolean signal which becomes false when a transaction occurs on S, and returns to true at time T after the transaction.

S'ACTIVE

is a signal whose value is true at exactly the transaction time when signal S might have been updated, and false otherwise.

S'TRANSACTION is unlike any of the event attributes. It is a signal of type BIT whose value toggles every time a transaction occurs on S.

S'LAST_EVENT

returns the length of time which has elapsed since the last change on S.

Can be used to compute time-varying values like capacitive dischange in a memory cell at refresh. Also another way to check signal stabilization.

Suppose we wish to compare the unsigned integer value of registers or buses. Relational operators are not defined on bit_vectors, but we can build comparators to do the work. If we wish to show high level algorithms using comparisons, we may define functions to provide relational operations on such things as bit_vector, MVL_vector, etc.

We may then choose to use the relational symbolsto describe (invoke) the new function. Replacing the function name with a quoted string (e.g. "<") creates an "overloaded" operator which can be used in the same syntactic way as the old or operation on bits and booleans.

Example: Declaration of Relational operation functions for bit_vectors.

        function  "<" ( x, y : bit_vector ) return boolean;

        function  "<=" ( x, y : bit_vector ) return boolean;

. . . etc. Now it is legal to write x < y

VHDL uses the type of the operand to choose whether to use this function to perform the operation, one of the operations already defined on integers and reals, or still another user-defined function.

Building Functions using Operator Overloading and Constant Arrays

Example

STD_LOGIC operators built using constant array declarations. In the package body of std_logic_1164 is:

------------------------------------------------     
-- local types 
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; 
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;

-- truth table for "xor" function 
CONSTANT xor_table : stdlogic_table := ( 
--  -------------------------------------------- 
--  | U   X   0   1   Z   W   L   H   -    --| |   
--  -------------------------------------------- 
    ('U','U','U','U','U','U','U','U','U'), --|U| 
    ('U','X','X','X','X','X','X','X','X'), --|X| 
    ('U','X','0','1','X','X','0','1','X'), --|0| 
    ('U','X','1','0','X','X','1','0','X'), --|1| 
    ('U','X','X','X','X','X','X','X','X'), --|Z| 
    ('U','X','X','X','X','X','X','X','X'), --|W| 
    ('U','X','0','1','X','X','0','1','X'), --|L| 
    ('U','X','1','0','X','X','1','0','X'), --|H| 
    ('U','X','X','X','X','X','X','X','X')  --|-| 
    ); 
-- truth table for "not" function 
CONSTANT not_table: stdlogic_1d :=  
--  -------------------------------------------- 
--  |  U   X   0   1   Z   W   L   H   -  | 
--  -------------------------------------------- 
    ( 'U','X','1','0','X','X','1','0','X' );  
------------------------------------------------     
-- overloaded logical operators     
------------------------------------------------     
FUNCTION "xor" (l : std_ulogic; r : std_ulogic )  
        RETURN UX01 IS 
    BEGIN 
        RETURN (xor_table(l, r)); 
    END "xor"; 
FUNCTION "not" (l : std_ulogic ) RETURN UX01 IS 
    BEGIN 
        RETURN (not_table(l)); 
    END "not";

Quoted"xor" to name the function creates an "overloaded" operator which can be used in the same syntactic way as the old or operation on bits and booleans. VHDL checks the type of the operand to determine what function is to be used.

Examples

Bit strings, in binary, octal, and hex notation. The underscore is legal and purely cosmetic.

constant  Zeros  : bit_vector :=  B"0000_0000" ;
constant empty:  bit_vector  :=  O"052";         
constant restart:  bit_vector:=  X"0FC"; 

-- Character string 
constant Error_Msg : string := "System Fries!!"

If the values of an enumerated scalar type are enclosed in single quotes, then one-dimensional arrays of the scalar type can also be shown in double-quoted strings.

Example: Since '0', '1', 'X', 'Z' are values for std_logic, we now can write string values for std_logic_vector.

constant ZZZs :  std_logic_vector := "ZZZZ_ZZZZ" ;

If the values are filled in name-by-name, the order is not important. This can be done both for arrays and records, although it is more common for records.

Form
constant_name := (name1 => value1, name2 => value2, . . . );

where names can be grouped A|B|C, and includes the reserved word OTHERS

 Examples

type clock_level is (low,rising,high,falling);
type ctable is array (clock_level) of bit;

constant conversion_table : ctable := ('0','1','1','0');
constant conversion_table : ctable := 
        (low=>'0', falling=>'0',high=>'1', rising=>'1');

constant conversion_table : ctable :=
        (low | falling=>'0',high | rising=>'1');
constant conversion_table : ctable := "0110";

type cpureg is MVL_vector (rsize-1 downto 0);
constant Zs : cpureg := (rsize-1 downto 0 => 'Z');
constant One : cpureg := (0 =>'1', others=>'0');

Initializing a Record

constant CLEARAX : Instruction := (opcode=>xor,  src_reg=>ax,
                                   dst_reg=>ax, src_mode=>reg,
                                   dst_mode=>reg);

        where 
                type Instruction is record
                        opcode  : Operations;
                        src_mode: Address_mode;
                        src_reg : Wordreg;
                        dst_mode: Address_mode;
                        dst_reg : Wordreg;
                end record;

and each of the types has been declared previously.

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Copyright 1998, Ben M. Huey
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.

Rev. 2/20/98 B. Huey