EE295 - ASIC Design Using VHDL

Advanced Topics

Assignment: Read Ch 8

Outline:

• Overloading
  • SubProgram Overloading
  • SubProgram Argument Types
  • SubProgram Parameters
  • Operators
    • Operator Argument Type Overloading
• Aliases
• Qualified Expressions
• User-Defined Attributes Was Discussed in the Attributes Lecture
• Generate Statements
  • Irregular Generate
  • Nested Generate
• Text I/O

Overloading

SubProgram Overloading

• Multiple SubPrograms Have the Same Name
• Which Makes Them Easy to Remember and Use.
• But Can Vary..
  • Number of Arguments
  • Type of Arguments
  • Return Value
• example:
  • --In a Declarative Region..
  • Type Address ..
  • Function counter ( clk, reset ) return address; --subtype of natural
  • Function counter ( clk, reset ) return std_logic_vector(0 to 11);
• • --In an Architecture
  • Signal fifo_addr : address;
  • Signal fifo : array ( address'range ) of data;
  • Signal delay_out : std_logic_vector ( 0 to 11 );
  • Begin
    • data_out <= fifo ( counter ( read_clk, read_reset ) );
    • --uses first counter
    • delay_out <= counter ( ext_strobe, reset );
    • U1:DRIVER ( D_IN => delay_out(0),..
    • U2:DRIVER ( D_IN => delay_out(1),..
    • U3:DRIVER ( D_IN => delay_out(2),..
    • --uses second counter
    • end;

SubProgram Argument Type Overloading

• Powerful Language Extension Feature
• Define

SubProgram Parameter Overloading

• Varying the Number of Parameters..
• Example:
  • Function parity ( d1, d2, d3 : bit ) Return bit;
  • Function parity ( d1, d2, d3, d4 : bit ) Return bit;
  • Function parity ( d1, d2, d3, d4, d5... : bit ) Return bit;

  Operator Overloading

  • Extends VHDL's Limited Native Operator Set
  • Results in Inherently More Readable, Understandable Designs
  • Define + ( plus ) sign for std_logic_vector
  • Impliment Signed/Unsigned Operations

  Operator Argument Overloading

  • Necessary for Flexible-to-Use Functions
  • Function "+" ( l : integer, r : std_logic_vector ) Return std_logic_vector is
  • Function "+" ( l : std_logic_vector, r : integer ) Return std_logic_vector is

  Aliasing

  • Useful Strategy for Presenting Alternative Views of a Design Object
  • Overcome Cumbersome Type Requirements
  • Example:
    • --In a Declarative Region
    • SIGNAL D_reg : bit_vector( 0 to 31 );
    • ALIAS DX_reg : bit_vector ( 0 to 15 ) IS D_reg ( 0 to 15 );
    • ALIAS DY_reg : bit_vector ( 0 to 15 ) IS D_reg ( 16 to 31 );

  Qualified Expressions

  • An Ambiguity Arises From Overloading
  • Because Operators and SubPrograms May Have Several Viable Argument/Result Types
  • And May be Combined With Other Operators and SubPrograms and So On..
  • VHDL Compilers May not be Able to Tell Which Version of a Function to Use From Context Alone.
  • ..Sadly, An Error Message Results
  • The SubProgram May Be Qualified With a Type
  • Syntax: SOME_TYPE'ambiguous_function --where some_type selects the desired function version
  • Forms (Constrains) an Unconstrained Assignment
    • TYPE numvec IS ARRAY ( 0 to 11 ) OF bit;
    • SIGNAL sum : numvec;
    • sum <= numvec'( others => '0' );
    • --forms an expression that is type compatable with the target object
    • --And Remains Type Compatable Through Updates to Type numvec

  Generate

  • We've Discussed This Earlier
  • But The Generate Bears Repeating (insert laugh here)
  • Concurrent Form of a Do-Loop
  • Create Copies of Concurrent Statements Like
    • Assignment of Arrayed Signals Using Variable/Offset Indexing
    • Component Instances in Regular Structures
  • Syntax
    • generation_scheme GENERATE
    • BEGIN
    • concurrent statements
    • END GENERATE;
  • The Iterative Form
    • ENTITY and_gate IS
      • GENERIC ( width : integer := 2 );
      • PORT ( a_in, b_in : in bit_vector( 0 to width-1);
      • z : out bit_vector(0 to width-1) );
      • ATTRIBUTE cell : boolean; --define attribute to pass downstream
      • ATTRIBUTE cell of entity and_gate is false; --tell design system this is not a
    • END and_gate; -- library cell.
    • ARCHITECTURE structural OF and_gate IS
    • BEGIN -- The generic contols how many
      • FOR i IN 0 TO width-1 GENERATE -- copies of AND_G get created
        • U1:AND_G PORT MAP ( A1 => a_in(i), B1 => b_in(i), Z1 => z(i) );
      • END GENERATE;
    • END structural;

  Irregular Generate

  • May Execute Conditionally
    • IF ( width < 4 ) GENERATE
      • U2:AND_G PORT MAP ( A1 => a_in(i), B1 => b_in(i), Z1 => z(i) );
    • END GENERATE;
    • IF ( width >= 4 ) GENERATE
      • U3:AND4_G PORT MAP ( A1 => a_in(i), A2 => a_in(i+1), A1 => a_in(i+2),
        • B1 => b_in(i), B2 => b_in(i+1), B3 => b_in(i+2),..
      • END GENERATE;

  Nested Generate

  entity load is
   port ( a, b : in std_ulogic_vector( 1 to 32 );
             x : out std_ulogic_vector( 1 to 32 ) );
  
  end load;
  
  architecture structure of load is
  constant fo_max : integer := a'high;
  signal load_sig : std_ulogic_vector ( 1 to fo_max );
  signal tie_up, tie_up_too : std_ulogic;
  component CHV2C
   port(
        P20                            :  out   STD_ULOGIC;
        P30                            :  out   STD_ULOGIC;
        P92                            :  out   STD_ULOGIC;
        P10                            :  inout STD_ULOGIC;
        PA0                            :  in    STD_ULOGIC;
        PE0                            :  in    STD_ULOGIC;
        PE2                            :  in    STD_ULOGIC);
  end component;
  --attribute PERF: string;
  --attribute PERF of CHV2C:component is "SAME";
  
  component CHIOA
   port( P10                            :  out   STD_ULOGIC);
  end component;
  begin
  tie_up <= '1';
  
  TIE:CHIOA port map ( P10 => tie_up_too );
  
  GEN_BLKS: for i in 1 to fo_max generate
    load_sig(i) <= a(i) and b(i);
  
    GEN_LOADS: for j in 1 to i generate
      DRVR1:CHV2C port map( PA0 => load_sig(i), PE0 => tie_up, PE2 => tie_up_too, P20 => x(i),
                   P30 => open, P92 => open, P10 => open );
    end generate;
  end generate;
  end;
  

  Text I/O

  The Base Language Posesses a Simple File Interface Usually Associated with Importing/Exporting Simulation Vectors.

  • Types:
    • Line is access String;
    • Text is file of String;
    • Side is ( Right, Left );
    • Width is Natural;
  • PreDefined Files
    • Input : Text is in "Std_Input";
    • Output : Text is out "Std_Output";
  • Procedures:
    • --For Fetching/Sending Next Line from/to File
    • procedure ReadLine ( F : in Text; L : out Line );
    • procedure WriteLine ( F : out Text; L : out Line );
    • --For Parsing/Building a Line into/From Design Objects
    • procedure Read ( L : inout; Value : out; |Good : out Boolean| );
    • procedure Write ( L : inout;..
    • Where Value May be of Type:
      • Bit, Bit_Vector
      • Boolean
      • Character
      • Integer
      • Real
      • String
      • Time
    • function endfile ( F : in File ) return Boolean;
  • Example:
    • --In Some Architecture's Declarative Region
    • File f : Text is in "~/cs295/labs/test.dat";
    • Begin
      • Process
      • Variable l : Line;
      • Variable b : Bit;
      • Begin
        • While Not Endfile( f ) Loop
          • Readline ( f, l );
          • Read ( l, b );
          • Read ( l, .. ;
        • End Loop;
      • End Process;
    • End Arc;

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  Copyright 1995, James Swift
  Copying this document without the permission of the author is prohibited and a violation of international cop>

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