--
-- Component : stopwatch
--
-- Generated by System Architect version v8.4_3.7 by mrmayer on Feb 9, 1997
-- LAST UPDATED by mrmayer on April 22, 1997
--
-- architecture data_flow is a structural model of the stopwatch
-- entity, using components for each of the drivers, state machines,
-- and memory entities.
--
LIBRARY ieee;  USE ieee.std_logic_1164.all;

ARCHITECTURE data_flow OF stopwatch IS
   COMPONENT disp_driver IS
    PORT (
      display_time : IN std_logic_vector (22 downto 0);
      indicator_mode : IN std_logic;
      sys_clk : IN std_logic;
      display_drv : OUT std_logic_vector (41 downto 0);
      indicators_on : OUT std_logic
    );
   END COMPONENT disp_driver;

   COMPONENT main_control IS
   PORT (
      set_reset : IN std_logic;
      start_stop : IN std_logic;
      sys_clk : IN std_logic;
      indicator_mode : OUT std_logic;
      pause_now : OUT std_logic;
      reset : OUT std_logic;
      run_timer : OUT std_logic
   );
   END COMPONENT main_control;

   COMPONENT switch_filter IS
      PORT ( 
         sr_pressed : IN std_logic;
         ss_pressed : IN std_logic;
         sys_clk : IN std_logic;
         sys_rst : IN std_logic;
         set_reset : OUT std_logic;
         start_stop : OUT std_logic
      );
   END COMPONENT switch_filter;

   COMPONENT timer IS
   PORT (
      reset : IN std_logic;
      run_timer : IN std_logic;
      sys_clk : IN std_logic;
      latch_out : IN std_logic;
      time_data : OUT std_logic_vector (22 downto 0)
   );
   END COMPONENT timer;

   COMPONENT internal_clock IS
      generic ( PERIOD : time );
      port ( clk: out std_logic);
   end component internal_clock;

   -- Internal Signals
   SIGNAL time_data : std_logic_vector (22 downto 0);
   SIGNAL indicator_mode : std_logic;
   SIGNAL set_reset : std_logic;
   SIGNAL start_stop : std_logic ;
   SIGNAL latch_out : std_logic ;
   SIGNAL reset : std_logic;
   SIGNAL run_timer : std_logic;
   SIGNAL sys_clk, invert_clk : std_logic;
   SIGNAL init, set_reset_init, start_stop_init : std_logic;  -- for sm

BEGIN
   -- to initialize state machine, uses jkff and bcd counter
   set_reset_init <= set_reset OR init;
   start_stop_init <= start_stop OR init;
   invert_clk <= NOT sys_clk;

   instance_internal_clock : COMPONENT internal_clock
      GENERIC MAP (10 us)
      PORT MAP (clk => sys_clk );

   instance_disp_driver : COMPONENT disp_driver
      PORT MAP ( 
         time_data,
         indicator_mode,
         sys_clk, 
         display_drv,
         indicators_on 
      );

   instance_main_control : COMPONENT main_control
      PORT MAP ( 
         set_reset_init,
         start_stop_init,
         sys_clk,
         indicator_mode,
         latch_out,
         reset,
         run_timer
      );

   instance_switch_filter : COMPONENT switch_filter
      PORT MAP ( 
         sr_pressed,
         ss_pressed,
         invert_clk,
         init,
         set_reset,
         start_stop
      );

   instance_timer : COMPONENT timer
      PORT MAP ( 
         reset,
         run_timer,
         sys_clk,
         latch_out,
         time_data
      );

END ARCHITECTURE data_flow;

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