LIBRARY ieee;   USE ieee.std_logic_1164.all;

entity d_latch is
   port ( clk : in std_logic;
          d : in std_logic_vector;
          q : out std_logic_vector );
   begin
     assert d'length = q'length
        report "D and Q not equal length in d_latch"
        severity failure;
end entity d_latch;

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