| DSP Track |
| Designing high-performance DSP systems for FPGA solutions |
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| Workshop 1 |
The FPGA Platform Radio: The Enabler for High-Performance Digital Communication Systems - Xilinx |
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Infrastructure equipment to support extended capability 3G, B3G (beyond 3G), 4G and JTRS military communication systems present many challenges in terms of business models, application overlays, and computational challenges related to high data rate requirements, advanced modulation (e.g. OFDM, MC-DS_OFDM, MC-OFDM), channel coding schemes (e.g. TCC, LDPC) and spatial diversity processing. To deliver flexible, future-proof and scalable hardware to the market, will require a new way of thinking about system design and partitioning, in particular, with respect to the device technologies that are utilized to service the multi-media, physical layer and baseband processing requirements. New generation systems will require arithmetic resourcing measured in the Tera- to Peta-op region. These considerations, in combination with the engineering challenges associated with building 90 and 65~nm silicon, requires a new way to think about system deployment. We are at a point in time that requires a re-thinking of traditional approaches to real-time high-performance signal processing.
This presentation provides an overview of field-programmable gate array (FPGA) signal processors and highlights how these platform-class devices provide a heterogeneous computing environment, rich in parallelism, and capable of servicing the most demanding of applications. A detailed study of an OFDM physical layer is presented. The case study is overlaid with the specific Virtex-II Pro™ and Virtex-4™ FPGA device features, as well as the algorithm approaches that are used to minimize the implementation footprint. Other key system considerations for dealing with power-amplifier (PA) linearization and PA operating efficiency are addressed through baseband digital pre-distortion and crest-factor reduction design examples.
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| Workshop 2 |
Accelerating DSP Design for FPGAs - Xilinx |
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State-of-the-art FPGAs provide the logic density and performance required of a high-performance signal processing platform, with dedicated silicon structures for arithmetic processing, high-bandwidth memory architectures, embedded microprocessors, and I/O. At the same time, their reprogrammability provides flexibility that allows optimization not possible in fixed architecture processors. Consequently, FPGAs have become key components for implementing extremely high-performance DSP systems, especially for digital communications and video applications.
However, mainstream design practice for FPGAs has historically mirrored that for application-specific integrated circuits (ASICs). A design is specified in a hardware description language (HDL) like VHDL or Verilog, which is used for both simulation and synthesis into vendor-specific FPGA and intellectual property (IP) libraries. Although HDLs provide significant control over the detailed behavior and implementation, the abstraction level is quite low. Consequently, the complexity of implementing a sophisticated high-performance FPGA is a significant barrier to wide adoption of FPGAs in signal processing.
In this session, we will demonstrate a high level abstraction design and verification tool that eliminates the need to work at the HDL level while still providing the quality of results that can be obtained by those proficient in HDL design.
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| Workshop 3 |
Accelerate High-Performance Real-Time Video & Imaging Applications with an FPGA and a Programmable DSP - TI |
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Broadcast infrastructure, teleconference, and video surveillance equipment must support various video compression standards (e.g. H.264/AVC, WMV-9, and MPEG-2) in different resolutions, profiles and levels. This requirement presents major design challenges to system architects, DSP, software and hardware engineers. We find that these individuals are increasingly relying on the industry standard media processors from Texas Instruments working in conjunction with Xilinx FPGAs to meet these demanding requirements.
We present a high-performance real-time video and imaging application reference design platform. The development platform is based on an add-on daughter card (XEVM642-2VP20) with a Xilinx Virtex2P20 device, that plugs onto the Texas Instrument's TMS320DM642 Evaluation Module. It offers an attractive development platform solution to engineers, by giving them access to the extremely powerful real-time signal processing capabilities of a Xilinx Virtex-2 Pro FPGA device coupled with the high-performance signal processing capability and the control functionality of a Texas Instrument's TMS320DM642 programmable DSP. We will illustrate the co-processing acceleration of an H.264/AVC high-definition (HD) and standard-definition (SD) encoder solution as an example. Next, we will demonstrate a MPEG-4 Simple Profile (SP) codec reference design solution on various software/hardware co-design platforms. Finally, we will show Xilinx System Generator design flow for video and imaging applications, and co-simulation capabilities under Matlab Simulink design environment with Xilinx FPGA and TI programmable DSP. Additional features will also enable system architects to work within a C/C++ software design flow and couple that with the flexibility and extremely high performance of FPGA hardware for the inner-loop functional blocks which require data-intensive real-time signal processing.
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| Workshop 4 |
Harness the Power of the Virtex-4 XtremeDSP Slice and Get the Highest-Performance DSP Functionality - Xilinx |
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This presentation will teach attendees how to implement high-performance, efficient FIR with the new Virtex-4 XtremeDSP™ Slices. We will demonstrate 500 MHz FIR filter implementations with the XtremeDSP Slice for common FIR filter architectures. The Xilinx XtremeDSP Slice contains all the components required to implement high-performance FIR filters with a minimum of fabric resources. Each XtremeDSP Slice implements an 18*18 bit signed multiplier and a 48-bit adder. In addition to the adder and multiplier, the XtremeDSP Slice includes optional input and output registers, support for dynamic operand muxing and symmetric rounding. These features enable FIR filters to be implemented entirely in XtremeDSP Slice columns, at full 500 MHz speed.
The presentation will detail implementations of numerous multi-rate, multi-channel and folded FIR filter architectures using the XtremeDSP Slice. Furthermore, the presentation will illustrate how other common DSP functions like Direct Digital Synthesizers, FFT butterflies, CIC and more can benefit from the new XtremeDSP Slice. Finally, two application specific case studies will demonstrate the advantages the XtremeDSP Slice and Virtex-4 bring to DSP.
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| Connectivity Track |
| Solving high-speed serial design challenges |
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| Workshop 1 |
Designing Serial Backplanes with Xilinx Solutions - Xilinx |
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As serial I/O technology starts becoming the norm, more and more designers are moving towards using it in their backplane designs to take advantage of the overall system cost savings. Designers can choose to implement serial I/O standards such as PCI Express, Advanced Switching, Serial RapidIO™, XAUI, Gigabit Ethernet and Fibre Channel either using proprietary architectures or standardized architectures such as AdvancedTCA™ in a multitude of topologies such as Star, Dual Star or Full Mesh. Xilinx offers a strong suite of solutions for designers of serial backplanes including its Virtex-4™, Virtex-II Pro™/Pro X FPGAs, IP and Reference Designs for implementing the serial protocols, an ATCA development platform, and signal integrity tools, training, support and services. This session will take the attendee through the emerging trends in serial backplane space, discuss design requirements, and describe the Xilinx solution and ways of using it. |
| Workshop 2 |
1-10 Gbps Serial Interconnect Requirements - Xilinx |
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Signal integrity considerations become very important when designing multi-gigabit serial channels from 1 Gbps to 10 Gbps and higher. For example, serial backplane channel designs have strict requirements for connectors, vias, pads, and transmission lines. This session will take the attendee through the mechanics of transmission line phenomena, describe the fundamentals of frequency dependent parameters, and inter symbol interference (ISI), including dispersion and pulse spreading. Using a serial backplane channel design example, capabilities and flexibility of the RocketIO MGT, including the pre-emphasis and equalization functionality, ability to compensate for channel parameters and meet design requirements will be discussed. |
| Workshop 3 |
10 Gbps Serial Backplanes using Virtex-II Pro X™ - Xilinx/Ansoft |
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Xilinx and Ansoft® have developed methods and guidelines for modeling 10Gbps interconnect on printed circuit boards (PCBs) and backplanes that utilize Xilinx Virtex-II Pro X FPGAs. Accurate electrical models that account for the physical effects encountered when designing at such high speeds have been created for the Xilinx Virtex-II Pro X IC package, microstrip and stripline transmission lines, connectors, and vias, using electromagnetic simulation. The full channel response, from the IC, through the package, onto the board and out the connecter was computed using Ansoft Nexxim® circuit simulation and system-level simulators. Parameterized models associated with this effort have been assembled into a 10Gbps backplane design kit that is available on the Xilinx "SI Central" website, enabling Xilinx customers to rapidly evaluate their own board designs and do what if analyses.
This presentation details the results of the Xilinx-Ansoft collaboration and will provide an overview of the 10Gbps design kit. Attendees will learn how to use the design kit for electromagnetic field simulation coupled with circuit and system simulation to predict performance of their circuit board designs. Ansoft will detail the methods for generating frequency- and time-domain results such as high-frequency insertion loss, TDR impedance plots, eye diagrams, and channel-to-channel crosstalk. The full channel simulations result in the insertion and return loss profiles as a function of frequency. Attendees will learn how to set parameters for output voltage swing, pre-emphasis, and equalization within the FPGA to overcome the predicted channel distortions.
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| Workshop 4 |
Addressing Integrated FPGA/PCB Design Challenges - Mentor Graphics |
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As FPGA devices increase in complexity, so does the system integration of the FPGA and PCB. Integration challenges can be broken down into two categories: system performance and designer productivity. System performance challenges are created by multi-gigabit simulation and timing closure requirements, as well as system design constraints, such as matched differential signal path routing. In addition, advanced PCB fabrication, including HDI/microvia structures and embedded passives, is another challenge that must be addressed to increase your systems performance.
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| Workshop 5 |
Xilinx Solutions for Next-Generation SONET/SDH Networks - Xilinx |
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Ethernet became ubiquitous and a de facto LAN (local area networks) protocol and is an ideal protocol for building cost-effective data networks. Ethernet bandwidth rates increased from 10Mb/s to 10Gb/s in less than a decade. Where as the optical transport, (both WAN and MAN) which is predominantly based on Sonet/SDH infrastructure, is built to transport the TDM traffic (voice). Data traffic exploded in the last 10 years due to the phenomenal success of the internet and now accounts for 90% of the total traffic. Original WAN protocols such as Frame delay, ATM, proved to be totally inadequate at these high Gigabit bandwidth rates due to scalability and inefficiency issues. Carriers/ILECs (Incumbent Local Exchange Carriers) wanted to evolve their transport networks to accommodate the higher bandwidths and prevalent data traffic while preserving their Sonet/SDH based infrastructure. Several protocols, such as PoS (Packet over Sonet), ITU-T Recommended X.85 (IP over SDH using LAPS) and X.86 (Ethernet over LAPS), were developed to efficiently transport the data traffic (Ethernet, IP) at high bandwidth rates on Sonet/SDH networks. While these are more efficient than original WAN protocols, they were protocol/traffic pattern dependant, and complex. This lead to the development of Generic Framing Procedure (GFP) protocol (ITU-T Recommendation G.7041), which defines a simple way to encapsulate data traffic independent of the LAN protocol and traffic pattern. GFP enables the scalable and efficient transport mechanism for all current, including Ethernet, Fiber Channel, Video Transport and ESCON.., and future data protocols on Sonet/SDH networks.
Xilinx silicon, IP and reference designs enable customers to implement SOC solutions for their next generation Sonet/SDH products. Xilinx solutions offer tremendous flexibility to the customers. Xilinx broad range of networking IP cores, including the GFP (new), Ethernet, Fiber Channel and SPI4.2, are proven and widely deployed, which allow customers to minimize the risk and reduce the product development time (hence Time To Market) significantly. This session focuses on Xilinx networking IP, especially the GFP core, and reference designs that are integral part of the Xilinx solution for next generation Sonet/SDH network products.
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| Logic Track |
| New tools, techniques and Virtex-4™ features to help you meet your functionality and timing requirements more quickly and easily than ever before |
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| Workshop 1 |
Memory Interface Solutions with Virtex-4 FPGAs - Xilinx |
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Faster, better, easier memory interface solutions - with the availability of faster memory technologies, new I/O standards are emerging. Design and verification solutions from Xilinx offer an ideal fit for memory interface applications. This session will show you how to easily design and verify high-performance memory interfaces for DDR2 SDRAM, DDR SDRAM, QDRII SRAM, RLDRAM II and FCRAM II. A detailed description of the memory reference designs will be presented followed by hands-on sessions using a memory controller code generator, memory interface development board and the in-circuit logic analyzer functionality of the ChipScope™ Pro. |
| Workshop 2 |
Dramatically Accelerate In-Circuit Debug of FPGA-Based Systems |
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Until recently, designers of FPGA-based systems often faced a manual and time-consuming process to make internal FPGA measurements with logic analyzers. This session will focus on a new timesaving Agilent logic analysis application, the FPGA Dynamic Probe, saving you days to weeks of development time. Attendees will participate in an interactive technical discussion that focuses on a new debug core that facilitates incremental internal FPGA measurements on new groups of internal signals without having to change or stop the design. New capabilities that the application delivers results in increased internal visibility yielding quicker time-to-market and a more robust design. The session will include a live demo that will show how to eliminate the tedious process of physically and logically mapping internal FPGA signal names to logic analyzer channels. Helpful hints and approaches for debug will be discussed. One or more examples from current users will be described to equip attendees to experience such timesaving themselves. |
| Workshop 3 |
Spartan-3 and Low-Cost FPGA Design Techniques |
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Learn design techniques that take advantage of Spartan-3 unique features to drive HIGHER device utilization and LOWER costs. This session will introduce you to features available in the Spartan-3 fabric that allow you to integrate more functionality on a smaller and less expensive FPGA. You will also learn how you can optimize your coding style to reduce the levels of logic in your design and take advantage of FPGA features to simplify your PCB layout. We will use specific examples - PicoBlaze design, FIR filter, Pulse Width Modulation (PWM) - to illustrate the device utilization and cost savings. |
| Workshop 4 |
Synplicity's Secret Recipes for Virtex-4 FPGAs - Synplicity |
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In this session, Synplicity will present software solutions for today's FPGA design challenges with a special focus on targeting Xilinx new Virtex-4 devices. This highly technical session provides an overview of the latest methodologies and techniques used for addressing timing closure, DSP optimization, debug, and using FPGAs for ASIC prototyping. Attendees can expect to learn how to improve timing closure through design planning and physical synthesis using Synplicity's Amplify FPGA product. In addition, attendees will learn about improving verification efficiency through RT Level debug using Synplicity's Identify product and a comprehensive prototyping solution using Synplicity's Certify product. |
| Workshop 5 |
Design Techniques to Maximize Performance and Minimize Area - Xilinx |
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Learn how your coding style and tools options can best utilize Xilinx FPGA resources. This session will demonstrate several HDL coding techniques to help you achieve the maximum performance from your FPGA with the most efficient design techniques specific to advanced features of the Virtex-4 device architecture. We will cover how to achieve your desired timing performance goals while minimizing device cost. This session will also provide an interactive look into PlanAhead, the new Xilinx hierarchical floorplanning tool, and how to improve design performance through high-level area planning and block-based incremental design. |
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| Processor Track |
| Comprehensive embedded solution for performance and flexibility |
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| Workshop 1 & 2 |
Implementation and Debug of a Dual PowerPC™ System with Floating Point
Co-Processor - Xilinx DOUBLE WORKSHOP (150 minutes) |
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With the advent of programmable platforms with embedded processors, designers now have the ability to create multi-processor systems with custom co-processors. Traditional means of debugging embedded systems in real time involve expensive hardware and software tools that may not provide the best result. Explore the power and ease of creating a dual PowerPC processor system with floating point co-processor, and Platform Debug using the Xilinx Platform Studio (XPS) IDE to debug software and hardware simultaneously. The presentation reviews PowerPC system architecture, illustrates how to implement the dual processor system using XPS Base System Builder, and then uses Xilinx ChipScope™ Pro to co-debug the custom hardware linking the two processors while watching software execution in the GNU Debugger (GDB). This reviews the common place problems encountered with hardware/software coherency control in digital design debugging, now made easier utilizing the cross trigger feature between GDB and ChipScope.
The available reference design serves as an EDK (Embedded Development Kit) template for your PowerPC design and debug environment.
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| Workshop 3 |
FSL - SW Acceleration with MicroBlaze™ for Implementation of Inverse Discrete Cosine Transform (IDCT) - Xilinx |
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Accelerating key functions within an embedded system can deliver a solution that is finely tuned to a designers need both in cost and performance. Learn how to use the Xilinx Platform Studio to design a highly optimized MicroBlaze system using the Fast Simplex Link (FSL) interface for high speed, multi-channel data acquisition in a Virtex™-4 LX or Spartan-3™ FPGA. This presentation will demonstrate from design conception through a bit file ready for download, the ease of designing with FSL and will demonstrate the means of accelerating critical functions within a design that can result in a smaller size when compared to a general bus-based system. The reference design presented illustrates at typical data acquisition task where multiple channels of rotational speed data from an automotive transmission stand tester must be simultaneously received and correlated with A/D and digital input information. The MicroBlaze system must calculate rotational velocity/acceleration and output a parallel stream of time-correlated data to system memory. Customize the reference design as a model for your application. |
| Workshop 4 |
Accelerating Development of RTOS-Based Embedded Systems with Integrated Embedded Tools - Xilinx |
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Xilinx has partnered with industry leaders in the embedded operating systems space, such as Wind River Systems, MontaVista Software, the Accelerated Technology division of Mentor Graphics, Express Logic, QNX Software, Micrium, and Mind NV to deliver their operating system support for our embedded PowerPC or MicroBlaze processors. Additional tool integration has been created with the Wind River Systems and MontaVista Software development flows to enable the quick creation of custom board support packages (BSPs). Xilinx continues to innovate with its embedded tools by providing Design wizards, Example Test Code, and IP creation and customization to shorten the learning curve and help automate and accelerate the embedded development process. This presentation will describe various methods on how an FPGA-based design can be created using these embedded tools. A demonstration using embedded Linux will be presented as an example. |
| Workshop 5 |
Ethernet Solutions with Xilinx Processors - Xilinx |
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Ethernet is the most widely-installed local area network technology. With the advent of embedded processors in FPGAs, designers can deploy complete Ethernet and TCP/IP based applications inside a single programmable logic device. Learn about how to jump start your next design using a variety of available hardware and software components provided by Xilinx and its partners. |
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