See Also

Counters use sequential logic to count clock pulses. You can implicitly implement a counter with a Register Inference. The Quartus^® II software can infer a counter from a Conditional ("If-Else") Statement that specifies logic that adds or subtracts a value from the signal or register. The Conditional Statement and additional logic must be inside an Always Construct that is sensitive to a posedge or negedge clock.

The example below shows a Verilog Design File (.v) that includes a variety of 8-bit counters, controlled by the clk, clear, ld, d, enable, and up_down signals, that are implemented with Conditional Statements.

module counters (d, clk, clear, ld, enable, up_down,
                qa, qb, qc, qd, qe, qf, qg,
                qh, qi, qj, qk, ql, qm, qn);

   input   [7:0] d;
   input   clk, clear, ld, enable, up_down;
   output  [7:0] qa, qb, qc, qd, qe, qf, qg;
   output  [7:0] qh, qi, qj, qk, ql, qm, qn;
   reg     [7:0] qa, qb, qc, qd, qe, qf, qg;
   reg     [7:0] qh, qi, qj, qk, ql, qm, qn;

   integer direction;

   // An enable counter
   always @ (posedge clk) begin
      if (enable)
         qa = qa + 1;
   end

   // A synchronous load counter
   always @ (posedge clk) begin
      if (!ld)
         qb = d;

      else
         qb = qb + 1;
   end

   // A synchronous clear counter
   always @ (posedge clk) begin
      if (!clear)
         qc = 0;
      else
         qc = qc + 1;
   end

   // An up/down counter
   always @ (posedge clk) begin
      if (up_down)
         direction = 1;
      else
         direction = -1;
      qd = qd + direction;
   end

   // A synchronous load enable counter
   always @ (posedge clk) begin
      if (!ld)
         qe = d;
      else if (enable)
         qe = qe + 1;
   end

   // An enable up/down counter
   always @ (posedge clk) begin
      if (up_down)
         direction = 1;
      else
         direction = -1;
      if (enable)
         qf = qf + direction;
   end

   // A synchronous clear enable counter
   always @ (posedge clk) begin
      if (!clear)
         qg = 0;
      else if (enable)
         qg = qg + 1;
   end

   // A synchronous load clear counter
   always @ (posedge clk) begin
      if (!clear)
         qh = 0;
      else if (!ld)
         qh = d;
      else
         qh = qh + 1;
   end

   // A synchronous load up/down counter
   always @ (posedge clk) begin
      if (up_down)
         direction = 1;
      else
         direction = -1;
      if (!ld)
         qi = d;
      else
         qi = qi + direction;
   end

   // A synchronous load enable up/down counter
   always @ (posedge clk) begin
      if (up_down)
         direction = 1;
      else
         direction = -1;
      if (!ld)
         qj = d;
      else if (enable)
         qj = qj + direction;
   end

   // A synchronous clear load enable counter
   always @ (posedge clk) begin
      if (!clear)
         qk = 0;
      else if (!ld)
         qk = d;
      else if (enable)
         qk = qk + 1;
   end

   // A synchronous clear up/down counter
   always @ (posedge clk) begin
      if (up_down)
         direction = 1;
      else
         direction = -1;
      if (!clear)
         ql = 0;
      else if (enable)
         ql = ql + direction;
   end

   // A synchronous clear enable up/down counter
   always @ (posedge clk) begin
      if (up_down)
         direction = 1;
      else
         direction = -1;
      if (!clear)
         qm = 0;
      else if (enable)
         qm = qm + direction;
   end

   // A modulus 200 up counter
   always @ (posedge clk) begin
      if (qn == 200)
         qn = 0;
      else
         qn = qn + 1; 
   end

endmodule

In the example above, all 14 Always Constructs with Event Controls are sensitive only to changes on the clock (clk) signal. All other control signals are non-clock synchronous controls.

The first Always Construct describes an enabled counter. A Conditional Statement uses the enable signal to control counter operation. At each rising clock edge (that is, posedge clk), the qa register is incremented by 1 and assigned to itself if the enable signal is 1.

Go to Implementing Registers for information on how to infer registers by specifying Conditional Statements in Always Constructs that are sensitive to clock edges.

The next 12 counters are described in the same manner. One or more Conditional Statement(s) use the enable, ld, d, clear, and up_down signals to control counter operation. The last counter uses the value 200 to control when the counter is reset to zero. At each rising clock edge, each of these counter registers is cleared; loaded with the value d; or incremented or decremented by 1, then assigned to itself based on the value of the control signal(s).

For more information, see the following sections of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual:

• Section 9.2: Procedural Assignments
• Section 9.4: Conditional Statements
• Section 9.7.2: Event Control
• Section 9.9.2: Always Constructs

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